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MosChip®
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Senior Physical Design Engineer

Senior Physical Design Engineer

MosChip®

3 years

0 Lacs

hyderabad telangana india

Posted:1 day ago| Platform:

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Skills Required

design engineering verification software mobility ai ml test automation logic circuit synthesis timing analysis dft power planning optimization routing checks drc logical lvs mentoring interface resolve communication extraction signal integrity cadence scripting perl

Work Mode

On-site

Job Type

Full Time

Job Description

Company Description:

MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with a workforce of over 1300 engineers based in Silicon Valley, USA, and India. Their engineering solutions range from end-to-end silicon design, verification, systems, software, and device engineering to multimedia, mobility, connectivity, AI/ML solution design, and test automation. MosChip® has an excellent track record with 200+ first-time right SoC tape-outs and has developed and shipped millions of connectivity ICs.

Role Description:

This is a full-time on-site role for a Senior Physical Design Engineer located in Hyderabad. The Senior Physical Design Engineer will be responsible for various tasks including physical design, physical verification, logic design, circuit design, and RTL design. Day-to-day activities include performing synthesis, place and route, timing analysis, and DFT implementation, ensuring designs meet performance, power, area, and manufacturability goals.

Qualifications:

He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
Minimum of 3-10 years of experience in physical design.
He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
Provide technical guidance, mentoring to physical design engineers.
Lead a team of Physical design engineers and be responsible for their blocks’ closure
Interface with front-end ASIC teams to resolve issues.
Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
Expertise in Timing closure on high speed interfaces is a plus
Excellent communication skills.
Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
Extensive experience and detailed knowledge in Cadence or Synopsys.
Expertise in scripting languages such as PERL, TCL.
Strong Physical Verification skill set.
Static Timing Analysis in Primetime or Primetime-SI.
Good written and oral communication skills. Ability to clearly document plans.
Ability to interface with different teams and prioritize work based on project needs.

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Senior Physical Design Engineer