Senior Physical Design Engineer

Company Description:

MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions with over 1300 engineers based in Silicon Valley, USA, and India. The company's solutions cover end-to-end silicon design, verification, systems, software and device engineering, multimedia, mobility, connectivity, AI/ML solution design, and test automation. MosChip® also focuses on developing Digital IPs, Verification IPs, Mixed Signal IPs, and Turnkey ASIC services. The company has an impressive track record with over 200 SoC tape-outs and millions of connectivity ICs shipped.

Role Description:

This is a full-time, on-site role located in Hyderabad for a Senior Physical Design Engineer. The Senior Physical Design Engineer will be responsible for end-to-end physical design tasks, including floor planning, placement, routing, and timing closure. The engineer will also handle physical verification processes, collaborate with logic and circuit design teams, and ensure the final design meets all specifications and requirements. The role involves close coordination with cross-functional teams to deliver first-time right silicon for complex SoC designs.

Qualifications:

• He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
• Minimum of 3-12 years of experience in SOC Physical design.
• He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
• Provide technical guidance, mentoring to physical design engrs.
• Lead a team of Physical design engineers and be responsible for their blocks’ closure
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
• Expertise in Timing closure on high speed interfaces is a plus
• Excellent communication skills.
• Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.