439 Physical Design Jobs - Page 11

About Tessolve Tessolve is a leading engineering solutions provider, enabling silicon and system companies to accelerate their products to market. With capabilities across silicon design, test engineering, and embedded solutions, we are an end-to-end partner for semiconductor companies globally. Job Description We are looking for a Senior STA Engineer with 8 10 years of hands-on experience in Static Timing Analysis for complex SoC/ASIC designs at advanced technology nodes (7nm, 5nm, or below). The ideal candidate should be technically sound, self-driven, and capable of independently owning STA tasks from RTL to signoff. Key Responsibilities Perform full-chip and block-level static timing analysis using tools such as Primetime , Tempus , or equivalent. Develop and validate timing constraints (SDC) for functional and DFT modes. Drive timing closure in collaboration with physical design, synthesis, and DFT teams. Analyze and resolve setup/hold, transition time, and cross-corner violations. Perform timing ECOs and timing model generation for hierarchical designs. Support signoff flows, including OCV, AOCV, POCV , and SI/IR-drop aware timing. Script automation in TCL/Perl/Python to improve STA efficiency. Participate in customer calls and support project execution in a global delivery model. Required Skills Strong fundamentals in STA, CMOS timing, and VLSI design concepts. Expertise in timing constraints, derating, and ECO implementation. Experience in hierarchical and flat STA at chip-level. Hands-on with timing sign-off methodologies across multiple PVT corners. Familiarity with clock domain crossing (CDC) and false path/multicycle path analysis. Working knowledge of physical design flows is a plus. Good communication and leadership skills. Educational Qualifications B.E/B.Tech or M.E/M.Tech in Electronics or related discipline. Nice to Have Experience with advanced technology nodes (5nm/3nm) . Familiarity with low-power design techniques (UPF) . Customer interaction and project leadership experience.

DIRECTOR OF MARKETING www.einfochips.com Job Description, Role Responsibilities POSITION TITLE: Engineer / Sr Engineer (Linux BSP) EXPERIENCE: 4-10 Years Role: Linux BSP LOCATION: Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore Company Profile eInfochips An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and Azure. Our work culture is built over years of experience in providing innovative solutions to our clients and our indomitable spirit to excel in all aspects of our engagement. We believe that our success lies upon the skills and quality of our people we work with. Silicon engineering services: ASIC / FPGA Design Development, Design Verification Validation, Physical Design DFT Embedded systems engineering services: Hardware Design, System Software, System Verification Validation, Multimedia Software engineering services: Cloud Enablement, IoT Mobility, Application Software, QA and Test Automation, BI and Data Visualization Extended services: New Product Development, Lifecycle Management, Product Sustenance IPs: DevOps for IoT, IoT Gateway Framework, IoT Device Lifecycle Management, Video Management Software, Reusable Camera Framework, Test Automation Framework, Reference Designs EVMs, Verification IPs, OptiX Physical Design Framework About Arrow Electronics Arrow Electronics (www.arrow.com) guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2021 sales of $34.48 billion, we develop technology solutions that improve business and daily life. Our strategic direction of guiding innovation forward is expressed as Five Years Out (Five Years Out | Arrow Electronics), a way of thinking about the tangible future to bridge the gap between what s possible and the practical technologies to make it happen. http://www.einfochips.com/ http://www.einfochips.com/ https: / / www.arrow.com / company / fiveyearsout / https: / / www.arrow.com / company / fiveyearsout / www.einfochips.com Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results- oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies. In addition, the right candidate will: Incumbent works under general supervision Incumbent has substantial experience to resolve problems and concepts Incumbent can work on complex concepts and implementation http://www.einfochips.com/ www.einfochips.com Be a highly energetic self-starter Be an open and excellent communicator Have exceptional interpersonal skills Be a consummate team player Interface well with Client Engineer Team members and other Business Units of eInfochips Finally, this individual must have an uncompromising level of personal integrity. Education A Graduate degree in Electronics and communication/Information Technology/Computer-Science is required. A Masters technical degree is highly desirable. Do you want to know more about usKindly click any of the following links based on your interest. Our Website: Click here Our Corporate Video: Click here Our Leadership Team: Click here Our Linkedin profile: Click here Our CSR Initiatives: Click here Our Life @ eInfochips: Click here Our Industry Recognition Awards: Click here Our Youtube archive: Click here OUR CORE VALUES a. Customer First b. Disciplined Execution c. Embrace Impossible Challenges d. Continous Learning e. . Product Services Company

Key Responsibilities: Lead end-to-end physical design flow for complex blocks or full-chip designs. Drive floorplanning, power planning, placement, CTS, routing, and physical verification (DRC, LVS). Optimize timing, power, and area to meet design specifications. Perform hierarchical/flat implementation based on project needs. Work closely with RTL, DFT, STA, and packaging teams. Manage and mentor a team of physical design engineers. Interact with EDA vendors to improve tool flows and resolve tool-related issues. Contribute to methodology improvements and script automation for design efficiency. Required Skills and Qualifications: B.Tech/M.Tech in Electronics/Electrical Engineering or related field. 8+ years of hands-on experience in physical design with deep expertise in block and full-chip implementation. Strong knowledge of EDA tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, RedHawk/Totem, etc. Solid understanding of STA, IR/EM analysis, congestion analysis, and ECO implementation. Experience on advanced nodes (7nm/5nm/3nm) is highly desirable. Prior leadership or team management experience. Strong debugging, scripting (Tcl, Perl, Python), and communication skills.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Senior/Lead PD Engineer ADI is looking for Senior/Lead PD Engineer for the development of complex mixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates. These SoCs involve multiple processor cores and speed signal processing hardware running at high speed. Position Requirements BTech/MTech degree in Electrical/Electronic from a reputed institute with 4-8 years of experience in the field of Digital place and route Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (22 nm, 16 nm, 7 nm, etc). Hands on experience in handling the tapeout of complex high speed SoC designs in cutting edge process technologies Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction Strong expertise in Static Timing analysis , constraint development and sign off. Innovate on the flows to meet the QoR targets and ensure predictability Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage. Being proficient in TCL, Perl etc.

THE ROLE: The Core design team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients / server) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Design of x86 Core microarchitecture features, power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Micro-architecting and documentation of the design features Mentor the junior members of the RTL team to meet the team goals Your commitment to innovating as a team member demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 11+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: Master s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance .

P MTS SILICON DESIGN ENGINEER (AECG ASIC PD Architect) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design architecture and flow development for next generation ASICs that meet Engineering, Business and Customer requirements. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Technical Physical Design lead on AECG ASIC solutions, focused on driving the best Power, Performance, Area for customers. Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase. Provide expert guidance to physical design execution teams within AMD and with external partners to drive delivery to customer commitments. Develop technical relationships with broader AMD Design/CAD community and peers. PREFERRED EXPERIENCE: Strong understanding of development of custom ASICs for external customers. Strong background in physical design with exposure to circuit and logic design. Proven track record of delivering SOCs in process technologies 7nm and below. Expert user of P&R, Timing and Physical verification tools from top EDA vendors. Proven expertise in developing physical implementation flows as required. Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design. Experience in leading a small team of high performing individuals. EDUCATION & EXPERIENCE: BS or MS degree in in Electrical Engineering or Computer Science. 16+years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

FELLOW SILICON DESIGN ENGINEER THE ROLE: We are looking for a Fellow-level Engineer to join our team to develop world-class Server products . In this role you will be engaged with Server SOC architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of Server products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology. THE PERSON: You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic. KEY RESPONSIBILITIES: Define and drive PPA uplift methodologies for Server products Develop and deploy end to end power optimization methodology for Physical Design Implementation Define PVT corners, device frequency scaling, frequency targets for next generation Servers in leading foundry technology nodes Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure . Hands-on experience in closing very high-frequency designs Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm Experience driving Physical Implementation methodology Excellent communication skills and strong collaboration across multiple business units PREFERRED EXPERIENCE: 20+ years experience in SOC Physical Design Implementation, Methodology, Signoff and TapeOut In-depth experience and deep conceptual understanding of domains like Full Chip Floorplanning, CTS, PnR, STA, PV, EMIR, Low power design, Logic synthesis, LEC/Formality, VSI, etc. Presentations, Papers and proven innovations, Patents in these domains is a strong plus Forward looking and dependable techincal leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper. Experience working seamlessly across engineering disciplines and geographies to deliver excellent results ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SK5 Benefits offered are described: AMD benefits at a glance .

THE ROLE: We are seeking a highly experienced and innovative SOC Physical Design Director to lead the development of Server SOC designs and very experienced physical design team . This senior level role is critical for the design development of Server SOC designs products at AMD and is responsible for delivering Server SOCs meeting challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: This role combines strong people leadership and teamwork skills driving cross functional teams across geographies. The person with strong technical expertise, Strong analytical and problem-solving skills working with both executive level technical and management leaders to influence and drive change. KEY RESPONSIBILITIES: Lead and manage a team of engineers focused on SOC Physical Design implementation and Signoff Bring deep knowledge and experience in Physical design & Timing closure and signoff and apply them to large, challenging, leading-edge Server SOC designs to ensure high quality on time delivery. Bring significant experience in effective team management to help mentor, coach and grow the Server SOC Physical Design Team with an emphasis on positive influence on team morale and culture Technically manage different aspects of Physical Design including Full Chip Floor planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off. Collaborate with cross functional teams between Architecture, Product planning, Packaging, IPs, CAD to drive SOC Implementation and PPA improvement. Experience and understanding of flow development and scripting. Strong Technical problem and debugging solving. PREFERRED EXPERIENCE: 20+ years experience in SOC Physical Design Implementation, Signoff and TapeOut Must have prior experience leading Physical Design teams of at least 50+ members Excellent analytical and problem-solving skills along with attention to details. Strong written and verbal communication, Time Management and Presentation Skills. Must be a self-starter, and able to drive independently and efficiently challenging and time critical tasks to on-time completion. Forward looking and dependable leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper. Experience in EDA tools for Physical Design and Signoff cycles - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk. ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Electrical Engineering #LI-SK5 Benefits offered are described: AMD benefits at a glance .

Video Editing Intern Jaipur (In-office) - Digi Spheres Video Editing Intern Jaipur (In-office) Job Summary: We re seeking a creative and technically skilled Video Editing Intern to bring our content to life. You ll be responsible for editing short-form and long-form content for various platforms. Key Responsibilities: Edit videos, reels, and motion graphics for client campaigns Add music, text, transitions, and other visual effects Optimize content for Instagram, YouTube, and other platforms Collaborate with content creators and strategists for ideation Requirements: Proficiency in Premiere Pro, Final Cut Pro, or CapCut Strong sense of pace, timing, and narrative flow

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and third-party vendor teams to continuously improve physical design methodologies and efficiencies. Qualifications: Minimum Qualifications: B.E/B.Tech or M.Tech/M.S Preferred qualifications: Requirements listed would be obtained through a combination of industry relevant job experience. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore

This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background. ASIC design experience with proven design background. Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment. Domain knowledge of at least one of the following protocols: PCI Express SERDES Serial ATA Good RTL and Gate Level simulation Debug skills Familiarity with Front end implementation like Synthesis, Static Timing Analysis, Logical Equivalence Check Preferred Experience Technical knowledge with any Interface IP such as PCIe, USB, SATA, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, and Implementation flows with Design Compiler, Fusion Compiler and PrimeTrime. Excellent organization skills, excellent communication skills and ability to interact with customers Proven track record in meeting tight schedules and handling multiple projects concurrently

An experienced and passionate Applications Engineer, ready to join our dynamic team. You thrive in fast-paced environments and are driven by the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI ) domain. With your strong technical background in ASIC design, you are adept at providing top-tier technical support and guidance. Your excellent communication skills enable you to effectively interact with customers and internal teams alike. You are not just looking for a job, but a place where you can make a significant impact and grow your career. What You ll Be Doing: Providing technical support to field engineers and customers utilizing Synopsys MIPI UFS Intellectual Property (IP) Partnering with high-tech customers through the full cycle of ASIC design, from installation and training to RTL design and production testing Conducting reviews on customers major SoC design milestones Authoring application notes and white papers to promote the IPs ease of use and address specific challenges Providing feedback to internal teams for continuous product improvements based on customer feedback Ensuring successful integration of Synopsys MIPI IP solutions into customers SoCs The Impact You Will Have: Enhancing customer satisfaction by providing expert support and ensuring seamless integration of Synopsys IP Driving innovation by collaborating with customers on cutting-edge SoC designs Contributing to the development of industry-leading IP solutions through continuous feedback and improvement processes Expanding Synopsys market presence in the MIPI domain through successful customer engagements Promoting the adoption of Synopsys IP by authoring impactful documentation and white papers Supporting the growth of Synopsys IP portfolio by identifying and addressing customer needs What You ll Need: Bachelors degree with 5+ years or Masters degree with 2+ years of relevant experience in the ASIC design process Proficiency in Verilog HDL, synthesis, simulation, and verification Knowledge of Place and Route, Design Reuse, Physical Design, or Analog Design is a plus Familiarity with MIPI UFS/UniPro protocols, high-speed SERDES, or parallel interfaces is advantageous Experience with Synopsys tool suites is a plus Strong verbal and written communication skills in English

Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers.

Notice Period : Immediate - 15 Days Key Responsibilities : - Software Development : Implement software solutions using Python programming language. - Test and Validation : Design and execute comprehensive test cases to ensure software quality. - Technical Documentation : Create clear and concise technical documentation. - Customer Support : Respond to customer inquiries and resolve issues in a timely manner. - Automation : Automate design steps within the VLSI CAD flow. - Agile Development : Work in Agile Scrum teams and follow Agile methodologies. - Collaboration : Collaborate with customers to align on project requirements and present project updates. - Quality Assurance : Adhere to coding standards and quality processes. Required Skills and Experience : - 5+ years of experience in software development. - Strong proficiency in Python programming language. - In-depth knowledge of object-oriented programming concepts. - Excellent understanding of Unix/Linux operating systems and shell scripting. - Experience with development tools like Git-BitBucket, JIRA, and Confluence. - Strong problem-solving and analytical skills. - Excellent communication and collaboration skills. Mandatory Skills : - Python Mandatory Expert 60m - Software Development Mandatory Expert 60m - Unix Mandatory Intermediate 48m - Cadence Optional Beginner 12m - Logical Physical Synthesis Optional Beginner 12m Highly Desired Skills : - Experience with CI/CD tools like Jenkins, GitLab, StockStorm, and Camunda. - Background in semiconductor, EDA, or tool development domains. - Experience working in Agile Scrum teams. - Understanding of VLSI CAD flows.

Key Qualifications Must have B.Tech or M.Tech with 4-7 years of relevant experience. Good knowledge of Physical design , STA , Physical Verification and Parasitic Extractionmethodologies. Proficiency in Unix, a strong understanding of ASIC design flow. Knowledge of Analog Mixed Signal flows will be an added advantage. Strong communication skills are a must. Proficiency in scripting languages - shell scripting, tcl, python would be helpful

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and motivated Physical Design Engineer with a passion for innovation and a proven track record in the semiconductor industry You thrive in dynamic environments and are adept at managing multiple projects simultaneously Your deep understanding of the full design cycle from RTL to GDSII, particularly in advanced FinFET nodes, positions you as a technical driver in your field You possess excellent communication skills, enabling you to effectively collaborate with cross-functional teams and stakeholders Your solid software and scripting skills, combined with your expertise in CAD automation methods, make you an invaluable asset to any project You are autonomous, capable of making timely judgments, and able to handle interruptions with ease, What Youll Be Doing: Driving the physical implementation of high-speed interface IPs and test-chips from SYN to GDS, Utilizing your software and scripting skills to enhance CAD automation methodology for the team Collaborating with multiple functional groups, including front-end, analog and CAD teams, Focusing on advanced SerDes developments, including the latest 112G/224G PAM4 standards, Leading the physical design team to ensure on-time delivery of projects, The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything, Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements, Reducing the risk and time-to-market for differentiated products, Driving technological innovation through advanced SerDes development, Enhancing Synopsys reputation as a leader in chip design and verification, Supporting the company's mission to power the worlds most advanced technologies for chip design and software security, What Youll Need: 10+ years of physical design experience with recent contributions to project tape-outs or IP delivery Strong tcl scripting skills in Place & Route Tools (Fusion Compiler / ICC2 / Others) Understand version control & have experience in one of the version control software (Perforce / Git / Svn / Clearcase) Experience with advanced FinFET nodes, TSMC 7 nanometer or below, Solid understanding of IC design, implementation flows, and methodologies for deep submicron design, Proven track record for technical steering of physical design teams for on-time delivery, Who You Are: Excellent communicator with the ability to engage with peer groups and customers, Autonomous and capable of making timely judgments, Proficient in software and scripting skills (Perl, Tcl, Python), Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs, Able to travel internationally as required, The Team Youll Be A Part Of: You will be part of a collaborative team within the Mixed-Signal IP organization, working closely with front-end, analog, and CAD teams The team focuses on the physical implementation of complex mixed-signal IPs and test-chips across multiple process technologies, with a specific emphasis on advanced high-speed SerDes platforms, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

What You ll Be Doing: * Serving as the single point of contact for post-silicon debug activities. * Enabling Product Requirement Documents (PRDs). * Working to enable IP as a product development platform. * Handling hands-on post-silicon test setups. * Collaborating on top-level physical design, board-level, and package-level designs. * Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: * Driving the successful development and deployment of PVT IP sensors. * Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions. * Ensuring high-quality product development through meticulous testing and debugging. * Contributing to the continuous innovation in chip design and software security. * Supporting Synopsys leadership in the market for PVT IP developments. * Empowering the creation ofhigh-performance silicon chips used in various advanced technologies. What You ll Need: * Hands-on experience in post-silicon test setups. * Sound knowledge of Digital/AMS chip design and post-silicon debug. * BS or MS degree in Electrical Engineering with 3+ years of experience. * Understanding of top-level physical design, board-level, and package-level designs. * Expertise in RTL development and physical design. Who You Are: * Strong communicator with excellent teamwork and interpersonal skills. *Detail-oriented with a mindset geared towards IP debug anddocumentation. * Proactive learner with the ability to adapt to new IPfunctionalities. * Effective leader with strong people management skills. * Highly motivated and capable of mentoring both internal teams and external customers.

Greeting with HCL Tech! We were looking somebody who is having experience in Physical design Experience: 4 to 10 Years Location: Kochi JD#1 : 4-6years Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks Good to have experience in TSMC/Intel lower technology node(16/14nm or below) Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build Basic Timing understanding to independently analyze timing paths Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage Basic equivalency check understanding. Good to have Conformal LEC experience. Should have understanding of basic shell scripting, tool based TCL scripting to automate redundant tasks JD#2 : 6-10years Tapeout experience in full chip floorplan/full chip partitioning flow. Experience in die-size estimation spread sheet IP based and synthesis based Experience in IO/Bump planning & placement, custom analog/PG planning and route implementation Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage Experience in RDL routing Experience in interfacing with cross functional teams and block PnR teams Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities Experience in version control systems Experience in managing/mentoring small teams

Project description The Engineer role provides the technical expertise and dedicated technical focus required to deliver on customer's next generation technology capabilities including data analytics, platform development, specialised application development, systems and processes. This role will operate predominantly in an Agile environment and such will be required to support the technology capabilities to effectively deliver value to customers. Responsibilities Complete the design, development and testing of components that deliver on technology capability with the goal of providing reliable, stable and operationally sound applications, systems and infrastructure that meet business requirements and industry best practices Design, configure and validate new and enhanced Systems needed to improve the flow solutions through our life cycles Specify interfaces and translate logical designs into physical designs taking account target environment, performance & security requirements and existing systems Quick POC development for technical solution feasibility using prototyping tools where necessary Employ a variety of emerging languages and tools to marry systems together. Ensure that applications are developed with consistent maintainable code which supports risk and compliance management Contribute to the continuous improvement of applications throughout lifecycle and provide technical input to the planning of future application and maintenance requirements Develop operational and system documentation to enable effective maintenance and support of applications Employ CI/CD and DevOps practices that are endorsed by Group Technology and ensure maximum leverage of existing platform services. Analyse business requirements and articulate complex technical requirements through collaboration with business users, technology groups and suppliers to ensure business requirements are understood by the technology group. Recommend and justify the functional design to address the business needs to ensure the business understands the proposed design Coordinate and participate in the analysis of Information Technology solutions to ensure effective solutions are delivered to the business. Skills Must have Avaloq Certified Professional (ACP) with 1-4 years' experience in customisation and implementation of Avaloq Banking System. 3+ years of work experience with banking or financial applications. Good understanding of banking operations, trade lifecycle and investment/ superannuation products. Good understanding of relational databases (preferably Oracle and PL/SQL) Subject matter expert of at least one Avaloq module (Functional and Technical) Strong skills with Avaloq development tools ICE and SQL Developer as well as Avaloq change life cycle. Prior Experience working with Avaloq Database Automation and Integration (ADAI) will be advantageous. Strong parameterisation skills in core Avaloq conceptsAvaloq scripts, Cost & Fees, Order Validations & workflow management, Book and Balance engines, Avaloq messaging interface (AMI), Task and Reporting framework. Understanding of Avaloq concepts such as EOD, Pillars and Rule loading. Experience with Avaloq smart client and functional understanding of various modules (Forms, Task and reporting desk, Central Services, Portfolio desk etc.) Ability to write scalable code adhering to Avaloq best practices. Understanding of SQL tuning and performance tuning of Avaloq codes through SQL Trace and PL/SQL Hierarchical Profile (HPROF) Understanding of Avaloq release management processes such as creating streams/releases and creating Avaloq packages for installation. Hands on experience in Avaloq release management processes and Unix scripting will be advantageous for an Avaloq release management role. Strong problem solving and troubleshooting skills of Avaloq banking system. Ability analyse Avaloq installation logs and underlying Oracle schema of ABS. Experience in raising / managing Avaloq kernel issues through Avaloq issue management tool. Nice to have - Other Languages EnglishC1 Advanced Seniority Regular

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Position - ASIC Engineer (5+ Years Floor planning , Place and route , Formal verification , Timing closure , Perl / Python / Scripting ) Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and best known methods to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experience. We are looking for high achievers who love challenging environment to join our team.

PMTS SILICON DESIGN ENGINEER THE ROLE: Should have 15+ years of experience in Physical Design methodologies and Fullchip Design. You have had significant success driving Fullchip Floorplan, Fullchip Place and Route , Fullchip timing. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead Physical Design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Should own and drive the Physical implementation and Full chip timing closure of multiple designs of next gen 3nm (or lower nodes) SOC. Role inovolves interaction with multiple design teams, CAD teams and Tool vendors (on and cross sites) Understand and drive the requirements, define the design implementation methodology, Resource allocation, Scheduling, Resource management and Risk management etc. Ability to learn, make progress and critical times and agility is preferred. Work closely with multiple Design teams for Area , Floorplan refinement and Timing targets PREFERRED EXPERIENCE: Should have 15+ years of experience in Physical Design methodologies , Fullchip Floorplan, Fullchip Place and Route, Fullchip timing signoff closure Automation skills TCL, Perl are must Should have experience with 3nm/2nm design methodology Should have lead team of 15 members and well versed with Tracking, Goal settings and Performance evaluations Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred

Experienced PD Engineer working on mutliple technology nodes. Design for 40/22nm analog, RF, and mixed/signal circuits will be an added advantage. Perform layout from scratch, modify existing layouts. Create block level floorplans and work within the constraints of higher-level floorplans. Participate in peer and engineering reviews. Provide accurate area and schedule estimates for assigned circuit blocks. Work closely with both design engineers and other layout engineers. Required Experience and Skills We are looking for an experienced person (~10-15 years) who has overall knowledge of PD and takes care of all the flows associated with it. Apart from PnR & Synthesis: Experience with work closer to the front end such as digital modeling, gate level simulations, CDC, LEC, and STA/synthesis. Floor planning: Strategically planning the placement of functional blocks on the chip. Placement and Routing: Optimizing the placement of components and connecting them with wires (routing). Timing Closure: Ensuring the chip meets timing requirements (ensuring signals arrive at the correct time). Power Integrity: Managing power distribution and ensuring the chip operates reliably. Verification: Checking the layout for errors and ensuring it meets design rules. ECOs: Implementing design changes (ECOs) to fix issues identified during verification. Flow Development: Participating in developing and improving physical design methodologies and CAD tools. Job Segment: Front End, Design Engineer, Drafting, Network, CAD, Technology, Engineering

THE ROLE: We are looking for an adaptive, self-motivative Physical Design Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading products to market. The Physical Design team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Physical Design Closure of critical partitions in complex IPs PREFERRED EXPERIENCE: 7+ years of expereince in Physical Design Should have done partition closure in at least 3-4 tapeouts Should have exposure to one of signoff verification flows ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering /Electronics Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance .

Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results- oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies.