439 Physical Design Jobs - Page 13

Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Preferred Qualifications: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Principal Duties and Responsibilities: Applies Hardware knowledge to assist in the planning, verification, and testing of electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Provides support for the integration of features and functionality into hardware designs in line with proposals or roadmaps. Assists in conducting simulations and analyses of designs as well as with the implementation of designs with the best power, performance, and area. Collaborates with team members to assist in the implementation of new requirements and incorporation of the latest test solutions. Assists in the evaluation, characterization, and development of manufacturing solutions for leading edge products in processes. Assists in the evaluation of reliability for materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Assists in the assessment of basic design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes technical documentation for Hardware projects. Level of Responsibility: Works under supervision. Decision-making affects direct area of work and/or work group. Requires verbal and written communication skills to convey basic, routine factual information. Tasks consist of a limited number of steps and can be referenced using directions or manuals. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog.

Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design and development cycles Synthesis, Static Timing Analysis and LEC of SoC/Cores Full chip and block level timing closure, IO budgeting for blocks Logical equivalence check between RTL to Netlist and Netlist to Netlist Knowledge of low-power techniques including clock gating, power gating and MV designs ECO timing flow Proficient in scripting languages (TCL and Perl). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 3-6 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Preferred Qualifications: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Principal Duties and Responsibilities: Applies Hardware knowledge to assist in the planning, verification, and testing of electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Provides support for the integration of features and functionality into hardware designs in line with proposals or roadmaps. Assists in conducting simulations and analyses of designs as well as with the implementation of designs with the best power, performance, and area. Collaborates with team members to assist in the implementation of new requirements and incorporation of the latest test solutions. Assists in the evaluation, characterization, and development of manufacturing solutions for leading edge products in processes. Assists in the evaluation of reliability for materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Assists in the assessment of basic design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes technical documentation for Hardware projects. Level of Responsibility: Works under supervision. Decision-making affects direct area of work and/or work group. Requires verbal and written communication skills to convey basic, routine factual information. Tasks consist of a limited number of steps and can be referenced using directions or manuals. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

General Summary: Qualcomm, a global technology leader, drives innovation to enable next-generation experiences and digital transformation for a smarter, connected future. As a Hardware Engineer, you will contribute to planning, designing, optimizing, verifying, and testing cutting-edge electronic systems including digital, analog, RF, optical circuits, FPGA, DSP, and system packaging. Working collaboratively with cross-functional teams, you will develop high-performance, power-efficient solutions that meet stringent performance and quality standards. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 3+ years of relevant experience. OR Master's degree in the above fields with 2+ years of relevant experience. OR PhD in the above fields with 1+ year of relevant experience. Key Skills & Experience: 5+ years of hands-on experience in static timing analysis (STA), constraint development, and physical design implementation. Proficient in industry-standard EDA tools such as PrimeTime (PT), Tempus, Genus, Innovus, and ICC. Deep expertise in STA debugging and fixing extreme critical timing bottlenecks. Skilled in preparing complex Engineering Change Orders (ECOs) for timing convergence across multiple process corners using tools like Tweaker, Tempus, and Physical PT ECOs. Strong understanding of power minimization techniques and experience implementing low power design methodologies. Experience with deep submicron process nodes preferred. Solid knowledge of high-performance and low-power implementation techniques. Proven ability to push Power, Performance, and Area (PPA) to achieve optimal design outcomes. Strong fundamentals in digital design and timing closure. Expertise in scripting languages such as Perl and TCL for automation and design tasks. Preferred Qualifications: Experience working with advanced process technologies and complex SoC designs. Ability to work in fast-paced environments and collaborate with multi-disciplinary teams. Strong analytical and problem-solving skills with attention to detail.

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams on next generation System-on-chip (SoC) for smartphone, tablet, automotive, machine-learning accelerators and other product categories. Minimum Qualifications: Bachelor/Masters Degree in Electronics & Communication / Micro Electronics or related field and 5+ years of Physical Design or related work experience. ORPhD in Electronics & Communication / Micro Electronics or related field and 2+ years of Physical Design or related work experience. Overview Work with Qualcomm's Platform Architecture team on next generation System-on-chip (SoC) for Compute, smartphone, IoT and other product categories. Candidate will be involved in architecture and/or microarchitecture of various subsystems and interfaces of the SoCs, e.g. reset, boot, power management, security, access control, debug services, various processing subsystems like CPU, DSP, GPU and AI Accelerator subsystems etc. The successful candidate will - Be part of Qualcomm Platform Architecture Team Work with Hardware and Software teams to understand the design requirements, specification, and interface details. Validate architecture/ microarchitecture models for multiple peripherals, interconnects, and IPs for Qualcomm SoC platforms. Work with team to integrate these models to the SoC platform and validate IP/ System Level use cases. Perform area, power, performance trade-offs and analysis of HW/SW re-usability requirements for IP/Cores and complete SoC. Develop Specification, system level architecture/micro-architecture of system use-cases, working with cross functional teams. Have experience working with ARM-based SoC architectures, in-depth understanding of computer architecture fundamentals, the ability to develop complex systems. Candidate will be working closely with cross-functional teams in analyzing power, performance, area trade-offs, IP wise Area deep dive analysis. will be involved in perform architectural analysis and architectural validation Individuals who possess skills/experience in one or more of the following are requested to apply: Minimum Qualifications: Good understanding of SoC Design & Physical Design Concepts. Understanding of VLSI flow from spec to tapeout Strong debugging, analytical and problem-solving skills Good understanding of interfaces and on-chip interconnects Proficiency in digital design, VLSI, computer architecture, HDL languages, Scripting languages (Perl/Tcl/Python preferred) ARM architecture, Coresight architecture, power management fundamentals Good communication skills, presentation skills and should manage his/her tasks independently Self-motivated, Go-getter & Strong inter-personal skills , Desired: hands on experience with SoC design and integration for complex SoCs Desired: Profiles with both Design and PD (SOC Floorplan/PKG/PDN) background is a big plus Desired: Python Scripting, Data visualization tools like XL - Pivot table, PowerBI Areas of Expertise (the more the better): Candidates should have one or more of the following areas of knowledge and/or expertise: Physical Design flow, understanding of design, floorplan & placement of different Digital/Analog components on an SOC Understanding of VLSI flow from spec to tape out with proficiency in digital design, HDL languages, Scripting languages is preferred. ARM and RISC-V Architecture expertise specifically in areas of Coherency, Signaling, Memory Management, Virtualization, etc DSPs, CPUs (ARM preferred), High and Low Speed peripherals DDR, Interconnect, System Cache, QOS. Power, Boot, Debug, Security, Access Control Architecture. Power and/or performance analysis, simulation, and modelling. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Physical Implementation activities for Subsystems whichincludes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strongexpertisein timing convergence of high frequency data-path intensive Cores and advanced STA concepts we'll versed with the Block levelPnRconvergence with Synopsys ICC2/ CadenceInnovusand timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issueswrtconstraints validation, verification, STA, Physical design, etc we'll versed withTcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills andgood communicationskills. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Bachelors/masters degree inElectrical/ElectronicEngineering from reputed institution 2-10years of experience in PhysicalDesign/Implementation

Key Responsibilities Execute full physical design flow for high-performance, low-power GPU cores, including floorplanning, placement & routing (PnR), clock tree synthesis (CTS), power planning, IR drop analysis, signal integrity, and timing closure. Perform multi-mode, multi-corner (MMMC) timing analysis and fix violations, implement ECOs, and ensure functional and design-for-test (DFT) constraints are met. Collaborate closely with design, DFT, and place-and-route teams to resolve constraint validation, verification, and physical design issues. Drive timing convergence and power, performance, and area (PPA) trade-offs in data-path intensive cores. Conduct formal and physical verification including DRC/LVS checks and power distribution network (PDN) analysis. Develop and maintain automated flows using scripting languages (Perl, Tcl) and shell scripting in Linux/Unix environments. Deliver physical design solutions aligned with project milestones while working collaboratively in a multi-engineer team. Minimum Qualifications Bachelor's degree or higher in Electrical/Electronics Engineering, Computer Science, or a related field. 4+ years of hardware engineering experience for Bachelor's degree holders, or 3+ years for Master's degree holders, or 2+ years for PhDs. Strong expertise with industry-standard physical design tools such as Synopsys ICC2, Cadence Innovus, PTSI, and Tempus in advanced technology nodes. Proven experience in physical implementation of high-performance GPU or similar complex cores, including timing closure and power optimization. Deep understanding of clocking architectures and advanced static timing analysis (STA). Proficiency in scripting languages (Perl, Tcl) and Linux/Unix shell scripting. Demonstrated ability to work effectively in team environments under project deadlines. Excellent problem-solving and communication skills. Preferred Qualifications 8+ years of experience in physical design/implementation. Prior experience working on GPU or high-speed digital cores. Hands-on experience with formal verification and physical verification flows.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 6-12 years of experience in physical design from product-based/EDA companies. DDRPhy /PCIE-high speed interface PD Timing Signoff experience with SNPS/CDNS tools PDNIR signoff and Physical verification knowledge Automation skills python/Perl/TCL RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff Proficiency in automation to drive improvements in PPA Experience working on multiple technology nodes in advanced processes. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Good to Have: Design level knowledge to optimize the implementation for PPPA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers

Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. Infra Systems Architect Infra Systems Architect for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. This position will be responsible for Technical leadership role working with SOC architects, DMs and PDMs from early stages of the project to understand new usecases and feature requirements IP baseline selection, area projections and feature negotiations Convert the requirements to solutions and work with Infra IP development teams to flawlessly implement them Point of contact in Product core and architecture meetings in identifying and solving system level issues. Work with performance projection team to define experiments, analyze data, draw conclusions, identify potential problems and drive solutions Work with SoC, Verification, Physical Design, SoC Floorplan and core teams in identifying optimizations and drive them into products. Point of contact for debugging Post Si issues at system level. Preferred Qualifications 15+ years of experience in SOC/IP architecture, micro-architecture and design. Good understanding of SOC. Possesses expertise in 1 or more of the following technical areas:DDR, Security, access control, Interconnects, SMMU, SOC power management, boot, clock/reset, UBWC, Encryption, ECC Understanding of ARM architecture (Coherency, bus interconnects, Security, arch evolution) Good communication and leadership skills; work with minimal supervision Collaborate with internal (Perf, Design and System team) and external (SoC arch, Client Ips) stakeholders in developing solutions Understanding of traffic patterns and BW of different clients a plus Experience with high-performance and low power micro-architecture concepts Experience with Verilog, logic design principles with timing, area and power implications. Experience with scripting languages like Perl/Python/Java for developing proof of concept of the new ideas. Performance:explore high performance strategies and validate that the micro architecture meets targeted performance. Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI. Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Good Understanding of concurrency, bandwidth, latency and system level aspects Provides direction, mentoring, and leadership from small to medium sized groups. Education Requirements:Bachelor s degree in Electrical Engineering required, Master's or Doctorate preferred

General Summary Qualcomm is a tech innovator focusing on next-gen products. Role involves planning, designing, optimizing, verifying, and testing various electronic systems including digital, analog, RF, optical, FPGA, DSP, and mechanical systems. Collaborate with cross-functional teams to meet performance and quality requirements. Support multiple SoC design teams in logic synthesis, power-aware synthesis (UPF), quality of results (QoR) optimization, and netlist signoff flows. Troubleshoot and debug synthesis/implementation issues. Develop and maintain third-party tool integrations and product enhancements. Evaluate new tools and refine methodologies for power, performance, and area (PPA) optimization. Minimum Qualifications Education: Bachelor's degree + 2+ years hardware engineering or related experience; OR Master's degree + 1+ year experience; OR PhD in relevant field (CS, Electrical/Electronics Engineering, etc.) Experience: 3 to 5 years experience in RTL design, UPF (Unified Power Format), physical-aware synthesis for advanced process nodes. Logic equivalence checking (LEC), scripting, and netlist timing signoff expertise.

General Summary Qualcomm is a technology leader pushing the boundaries to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will design, optimize, verify, and test electronic and mechanical systemsincluding Digital/Analog/RF/optical circuits, packaging, test systems, FPGA, and DSP systemsto deliver cutting-edge products. You will collaborate across teams to meet performance goals and product requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of hardware engineering experience, OR Master's degree with 2+ years of experience, OR PhD with 1+ year of experience. Role: IPPD Physical Design Engineer You will engage in physical implementation activities for high-performance CPU cores at advanced technology nodes (16/14/7/5 nm or below), including some or all of: Floor-planning Place and Route Clock Tree Synthesis (CTS) Formal Verification Physical Verification (DRC/LVS) Low Power Verification Power Delivery Network (PDN) Timing Closure Power Optimization Required Skills and Experience Hands-on experience with physical design implementation of performance, power, and area (PPA) critical cores. Expertise in timing convergence of high-frequency, data-path intensive cores and advanced static timing analysis (STA) concepts. Proficient in block-level place-and-route convergence using Synopsys ICC2, Cadence Innovus, and timing closure using PTSI/Tempus on latest technology nodes. Solid understanding of clocking architecture. Familiarity with scripting languages such as Tcl, Python, or Perl for automation tasks. Strong problem-solving skills, good communication, and effective teamwork capabilities. Ability to collaborate with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and physical design.

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Principal Duties and Responsibilities: Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

General Summary Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will: Plan, design, optimize, verify, and test electronic systems. Work on yield bring-up, circuits, mechanical systems, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaborate with cross-functional teams to develop solutions and meet performance requirements. Contribute to launching cutting-edge, world-class products. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of relevant hardware engineering experience, OR Master's degree in the above fields with 1+ year of relevant experience, OR PhD in the above fields. Additional minimum qualifications include: Bachelor's degree in Science, Engineering, or closely related field. Experience with digital design and RTL development. Experience using front-end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality, and Synopsys PrimeTime. Preferred Qualifications Knowledge and experience in graphics design and development. Proficiency in scripting languages such as Perl, TCL, and shell scripting. Strong interpersonal and teamwork skills with the ability to work independently. Ability to solve complex, unique, and detailed technical problems. Familiarity with the latest EDA tools for synthesis, formal verification, timing analysis, and physical design.

General Summary NUVIA, now a part of Qualcomm, is on a mission to reimagine silicon and develop computing platforms that redefine industry standards. We're building custom CPUs that lead the industry in power, performance, and scalability. As a CPU Physical Design CAD Engineer , you will be instrumental in developing and supporting advanced implementation tools and flows that ensure our silicon achieves best-in-class Power, Performance, and Area (PPA). This is a unique opportunity to work alongside some of the most talented engineers in the world, driving cutting-edge innovations in physical design and EDA tooling. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 6+ years of hardware engineering experience OR Master's degree in a relevant field and 5+ years of experience OR PhD in a relevant field and 4+ years of experience Roles and Responsibilities Develop, integrate, and release new features in high-performance place-and-route CAD flows Architect and recommend methodology improvements to optimize power, performance, and area Maintain and debug implementation flows , resolving project-specific issues Collaborate with global CPU physical design teams, offering methodology guidance and tools/flow support Partner with EDA vendors to define roadmaps and resolve tool issues Preferred Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science 10+ years of hands-on experience in place-and-route for high-performance chips, either in CAD or design roles High proficiency in Tcl and Python scripting Experience in automation of CAD and physical design tasks Familiarity with a broad range of Physical Design tasks , including place-and-route, timing analysis, and physical design verification (PDV) Experience working with advanced technology nodes (e.g., 5nm and below) Strong understanding of digital design, timing analysis, and physical verification Proficient with industry-standard tools such as Cadence Innovus Demonstrated success in managing and regressing place-and-route flows

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are seeking a dedicated and skilled EM/IR Methodology Engineer to join our team. The role involves developing and maintaining methodologies for Electromigration (EM) and Voltage Drop (IR) analysis to ensure robust and reliable designs in advanced semiconductor technologies. The ideal candidate will work closely with cross-functional teams to optimize power delivery networks and ensure design compliance with EM/IR standards. Key Responsibilities: Develop, validate, and optimize methodologies for Electromigration (EM) and Voltage Drop (IR) analysis for advanced semiconductor designs. Collaborate with design, CAD, and physical implementation teams to optimize power delivery networks. Enhance and automate workflows to improve PDN analysis efficiency. Partner with EDA tool vendors to enhance and customize EM/IR analysis tools. Support design teams in EM/IR verification and sign-off. Required Skills and Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or a related field. 3-5 years of experience in EM/IR analysis or physical design methodology. Strong understanding of Electromigration (EM) and Voltage Drop (IR) concepts and their impact on circuit reliability. Hands-on experience with EM/IR analysis tools such as Voltus , RedHawk , Totem , or equivalent. Preferable if worked on 2.5D/3D-IC , CoWoS technologies. Exposure to AI/ML concepts will be bonus. Proficiency in scripting languages such as Python , Perl , or Tcl to automate workflows. Good understanding of STA concepts. Strong problem-solving and analytical skills. Excellent communication and teamwork skills.

We are seeking an experienced ASIC Physical Designer to join our team in Hyderabad. The successful candidate will be responsible for designing and implementing complex ASICs, ensuring timely and efficient physical design closure.

Job Title: Lead RTL to GDS Engineer Block/Sub-System Level Company: Wafer Space an ACL Digital Group Location: Bangalore, India Experience: 7+ - 20+ Years Notice Period: Immediate to 30 Days Compensation: Best in Industry Overview: Wafer Space, part of ACL Digital , is actively hiring a Lead RTL to GDS Engineer with deep expertise in block/subsystem-level physical design and signoff for advanced SoC designs (7nm and below). The role involves leading full RTL to GDSII implementation, owning delivery, mentoring junior engineers, and collaborating across functions. We’re looking for professionals who are passionate about driving execution quality, solving complex physical design challenges, and making impactful contributions in high-performance silicon projects. Key Skills & Responsibilities: Technical Responsibilities: Lead end-to-end RTL to GDSII implementation at block/subsystem level. Perform synthesis, floorplanning, placement, CTS, routing, and optimization for PPA. Full signoff closure experience including: Static Timing Analysis (STA) Physical Verification (DRC/LVS using Calibre) IR drop, Electromigration (EM), Crosstalk Drive low power design closure using UPF/CPF flows . Debug and resolve complex design and convergence issues. Collaborate with RTL, DFT, verification, and packaging teams for integration and handoff. Guide flow/methodology improvements and automation scripting (TCL, Python, Perl). Leadership Responsibilities: Provide technical leadership and mentorship to junior engineers. Conduct design reviews and drive quality across the team. Interact with program managers and cross-functional teams to ensure timely delivery. Key Skills: RTL to GDSII implementation Block & Subsystem level design STA (PrimeTime/Tempus) Synthesis (Design Compiler/Fusion Compiler) Place & Route (ICC2, Innovus) Calibre DRC/LVS RedHawk / Voltus (IR/EM analysis) Low power design (UPF/CPF) Scripting (TCL, Python, Perl) Tape-out experience at advanced nodes (7nm, 5nm, 3nm) Team leadership & technical mentoring Preferred Experience: Experience with TSMC, Samsung, Intel process nodes. Hands-on tape-out experience at FinFET nodes (5nm and below). Background in SoC integration and hierarchical design. Why Join Wafer Space – an ACL Digital Group? Work on cutting-edge SoC designs and the latest technology nodes. Be part of a highly technical and collaborative team. Best-in-industry compensation and growth opportunities. Lead from the front and make a real impact in semiconductor innovation. If this opportunity isn’t for you, please share or refer someone in your network who would be a great fit. Referrals are highly appreciated! (prabhu.p@acldigital.com)

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Place and Route. Experience1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.