439 Physical Design Jobs - Page 10

The focus of this role is in developing clocking strategies that meet stringent timing, power, and area constraints while managing clock distribution across the SoC. THE PERSON: As the SoC Clock Design Lead, you will be responsible for the architecture, design, and optimization of clocking structures within complex SoCs. This position involves working closely with cross-functional teams, including RTL, physical design, power, and timing engineers, to ensure efficient and high-performance clock networks. KEY RESPONSIBILITIES: Proficiency in clock tree synthesis (CTS) and clock network optimization using tools like Synopsys FC, ICC2. Strong experience in static timing analysis (STA), clock domain crossing (CDC) checks, and jitter/skew analysis. In-depth knowledge of clock gating, power optimization, and low-power design techniques. Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancements Familiarity with advanced technology nodes (5nm and below) and their specific challenges in clock design Understanding of signal integrity, electromigration, and power integrity in the context of clock networks. PREFERRED EXPERIENCE: Define and implement the clock architecture and distribution strategy for SoCs, optimizing for performance, area, and power requirements. Lead clock tree synthesis, insertion, and optimization to achieve timing closure and reduce clock skew/jitter across the SoC. Implement and validate clock gating techniques to minimize dynamic power consumption and enhance SoC energy efficiency Work with RTL, timing, power, and PD teams to resolve clock-related issues, optimize clock distribution, and ensure alignment with SoC design goals Create and maintain custom scripts in Perl, Python, or Tcl to automate clocking tasks, streamline workflows, and improve productivity ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering.

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

We are looking for a talented and highly motivated research scientist to help advance our efforts in AI4Code, specifically focusing on testing and validation. In this role, you will work at the intersection of AI, software engineering, and testing, leveraging state-of-the-art techniques to enhance automated code analysis, test generation, and defect detection. You will collaborate with a multidisciplinary team to develop and deploy AI-driven solutions that improve software quality, reliability, and maintainability. Required education Doctorate Degree Preferred education Doctorate Degree Required technical and professional expertise Deep expertize in program analysis, formal verification. Proficiency in Python, Java, or other relevant programming languages. Familiarity with machine learning, NLP, or AI-driven software analysis. Experience with test frameworks, static analysis tools, or automated testing methodologies. Solid understanding of data structures and algorithms to enhance test generation and analysis. Passion for AI-driven innovation in software engineering Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

You Are: You are an experienced and initiative-taking individual with a strong technical background in STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What Youll Be Doing: * Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * Developing Digital BE activities includes synthesis, pre-layout STA, SDC constraints development, placement, CTS, routing and collaborating with the different functional teams to achieve optimal design solutions. * Post layout STA, timing & functional ECO development, timing signoff methodology at higher frequency IP designs closure. * Co-work with Place & Route team to resolve full chip/IP/block level layout integration issues to drive timing closure. * Coordinates with internal RTL IP owners on constraints related issues. * Creating new flows/methodologies and updating existing ones through collaboration with architects, Physical design and RTL design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. * Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation in STA and signoff design methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: * BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience. * Strong PD, pre& post layout STA and signoff experience, including SDC development, Mutli mode design development experience. *Experience in functional, test (shift, capture and at-speed ) constraints development experience and timing closure with MCMM is mandatory. * Experience in generating ECO for DRV cleaning and timing closure is mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/PT/PT-PX * Sound understanding of Physical design, STA and signoff concepts. *Proven track record of successful timing closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...) *Good understanding of OCV, POCV, derates, crosstalk and design margins. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providing physical design and signoff solutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals.

Long Description Annual maintenance contract preparation and preventive maintenance of QC and IPQA instrument as per approved procedure. Breakdown handling of QC and IPQA instrument as per approved procedure. Upkeep the records of preventive maintenance and breakdown in SAP. Qualification of new instruments and SOP preparation. To participate in failure investigation related to malfunctions. To impart training to the analysts for instruments maintenance and troubleshooting. Co-ordination with vendor service engineer of service /breakdown related activities. To maintain GMP in QC laboratory, Real time documentation. Computer system validation of laboratory instruments. Execution and implementation of quality system in laboratory. Taking part in internal calibration, out-side calibration and reviewing calibration data. Taking part in instrument cleaning maintain & Maintenance of all laboratories indents. QAMS, Caliber-e-log related activities SAP Bill & invoice clearance PO & PR related activity software handling EDMS ,SAP, caliber E log, QAMS, LIMS. etc. Competencies Innovation & Creativity Result Orientation Collaboration Customer Centricity Developing Talent Stakeholder Management Strategic Agility Process Excellence Education Graduation in Mechanical Engineering Work Experience 7 to 8 Years of experience in Quality Control as Instrument Engineer

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks. What you ll be doing: Own micro-architecture and RTL development of design modules. Micro-architect features to meet performance, power and area requirements. Work with HW architects to define critical features. Collaborate with verification teams to verify the correctness of implemented features. Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 7+ years of design experience. Experience in RTL design of complex design units for at least two or three projects. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Leadership experience in leading small 2-3 member teams. Good interpersonal skills and ability & desire to work as a part of a team. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. #LI-Hybrid

As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design and implementation of advanced semiconductor chips. Working closely with RTL designers, physical design teams, and other cross-functional groups, you will be responsible for full-chip floor planning, enabling efficient design layouts, and optimizing the placement of major functional blocks. This position requires a solid understanding of physical design and chip architecture, as we'll as experience in floor planning tools and methodologies for high-performance and low-power design. Technical Requirements Proven experience in top level floor planning/block partition which includes physical partition, pin/feedthrough placements and repeaters assignments. Experience in SOC floorplan aspects like FullChip clock spine distribution, analog integration, push down macros, GPIOs. Proficiency in EDA tools such as Cadence, Synopsys ICC, Calibre, etc Strong scripting skills in Tcl, Perl, or Python for automation In-depth knowledge of upf, floor planning concepts, including chip partitioning, placement, and routing methodologies. Experience with power, timing, and area optimization techniques Familiarity with design rule check (DRC) requirements. Responsibilities Lead the floor planning process from RTL to GDSII, optimizing block placement, chip partitioning, and routing feasibility to ensure timing, power, and area constraints are met. Collaborate with RTL, block-level, and physical design teams to integrate IPs, macros, and other design components efficiently at the top level Work on area and power optimization techniques to achieve a highly efficient chip layout. Perform what-if analyses to evaluate trade-offs and optimize design parameters. Interface with architecture, package, and timing teams to align on chip-level requirements and ensure the physical design meets performance and design intent. Identify potential design issues early in the floor planning process and collaborate with stakeholders to develop and implement mitigation strategies Develop, enhance, and maintain custom scripts to automate repetitive tasks within the floor planning flow, ensuring efficiency and accuracy.

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible„¢ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

1. Lead High Performance ARM Core Hardening Job Title: Lead Engineer ARM Core Hardening Location: BLR/Hyd Experience: 812 years Technology Node: 5nm/3nm/2nm FinFET/GAA Reports To: Director/Technical Manager SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster). Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy. Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff. Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization. Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture. Interface with foundry and EDA vendors for process tech enablement and tool issues. Technical Skills: Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache). Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem. Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS. Experience with UPF-based low power flows and Conformal Low Power (CLP) verification. Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement). Familiar with physical architecture trade-offs (voltage islands, power domains, channel management). Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores. Experience taping out at 5nm or lower is mandatory. --- 2. Engineer ARM Core Hardening Job Title: Physical Design Engineer ARM Core Hardening Location: BLR/Hyd Experience: 38 years Technology Node: 5nm/3nm/2nm FinFET/GAA Key Responsibilities: Implement physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic. Perform static timing analysis, IR/EM validation, and physical verification. Optimize for frequency, leakage, and area within power and thermal budgets. Support integration of hardened cores into SoC top-level environment. Technical Skills: Good understanding of ARM core architecture and pipeline structure. Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk). Experience in UPF flows, CPF/UPF constraints, and low-power verification tools. Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs. Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC. Familiar with scripting (TCL, Python, Perl) to automate flows and reports. Work Experience Lead High Performance ARM Core Hardening Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP. Worked with multi-core cluster hardening and coherent interconnects (e. g. , CMN-600). Experience with RTL-based performance modeling and correlation with implementation ARM Core Engineer: ARM POP usage experience. Previous tapeout at \u22647nm. Exposure to hierarchical and multi-voltage designs. Familiarity with advanced floorplanning constraints for multi-core clusters.

Full time with century old top Japanese MNC JOB SUMMARY ( Full time with Super Top Japanese MNC) JDs follow for following roles, Principal Engineer VLSI Semiconductor Chip Design Analog Principal Engineer VLSI Semiconductor Chip Design Backend Principal Engineer VLSI Semiconductor Chip Design Frontend ------------------------------------------------------------------------------------------------------------------------------------------ Job Title : Principal Engineer Chip Design Analog Job Title: Principal Engineer - Analog IP/IC Job Overview: As an Principal Engineer - Analog IP/IC specializing in Semiconductor Chip Design, you will lead and coordinate the execution of analog and mixed-signal integrated circuit development projects. This role requires a strong technical background in analog design, verification, and physical implementation, coupled with exceptional project management skills. You will oversee teams engaged in designing high- performance analog circuits, ensuring precision and reliability in semiconductor designs. Key Responsibilities: Design analog/mixed-signal blocks: ADC/DAC, PLL, LDO/DCDC, IO, Motor & Gate Drivers . Run MATLAB modeling , circuit simulations , and post-layout analysis (LPE, Monte Carlo). Develop and manage verification plans , mixed-signal simulation , and behavioral models . Guide custom layout and ensure DRC/LVS/ESD/DFM compliance. Collaborate with digital, verification, layout, and test teams. Use industry-standard EDA tools (e.g., Custom Compiler). Product Support Required Skills & Experience Required Skills & Experience Min 8+ years of experience in custom analog/mixed signal design Strong in variation-aware design, verification planning, and cross-functional teamwork. Layout Parasitic Extraction (LPE), Custom IC Design, EDA Tools for Analog Design Strong design and debugging skills. Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience Min 1+ years of Project Management (Waterfall and Agile Hybrid Methodology). Continuous Improvement. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field ------------------------------------------------------------------------------------------------------------------------------------------------------ Job Title : Principal Engineer Chip Design Back End Job Overview: : As a Backend (Physical Design) Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding of semiconductor processes, and exceptional project management skills. You will oversee teams engaged in physical design, synthesis, DFT, place and route, power integrity, and other back-end aspects to ensure the successful realization of semiconductor designs. Additionally, you will oversee product support activities for both Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. Key Responsibilities: Technical Leadership - Own synthesis, SDC constraint development, and formal verification. - Drive place & route (P&R) including floorplanning, CTS, and timing closure. - Optimize for power, performance, and area (PPA); manage power distribution and multi-voltage design. - Lead STA across corners/modes and support technology node migration. - Integrate and verify SCAN/MBIST, define test specifications, and debug test coverage issues. - Perform DFM, DRC, and ESD checks to ensure manufacturability. - Collaborate with cross-functional teams (Frontend, Analog. - Document design flow, participate in design reviews, and mentor junior team members. - Product Support and RMA support Required Skills & Experience - Min 8+ years of strong experience in backend flows for MCU or low-power SoC designs . - Ability to lead the DFT teams, Physical and formal Verification Teams. - Exposure to frontend and Analog processes. - Ability to collaborate effectively with frontend and analog teams - Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience - Min 1+ years of Project Management (Waterfall and Agile Hybrid Methodology). - Continuous Improvement. - Knowledge of industry standards and best practices in semiconductor front-end design. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field. ---------------------------------------------------------------------------------------------------------------------------------------------- Job Title : Principal Engineer – Chip Design Front End Job Overview: As a Frontend Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification, and project management skills. Additionally, you will oversee product support activities for both the Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. Key Responsibilities: Technical Leadership and Architecture Design Architecture from scratch for new products and understand the specifications of the derivative products. RTL Design and Coding, Code Quality Management : Creating RTL Design and Coding.. Ensure highest quality by applying suitable coding standards and other techniques. Design Verification : Ensuring the correctness and functionality of the design through rigorous verification processes. This includes creating test benches, running simulations, and debugging the design. Collaboration : Working closely with other teams, such as physical design, analog IP/IC, software, and system engineering teams, to ensure seamless integration and functionality of the final product. Mentorship and Leadership : Leading and mentoring junior engineers, providing guidance on best practices, and ensuring the team adheres to project timelines and quality standards. EDA Tools Proficiency : Utilizing EDA tools for design, simulation, and verification tasks. Documentation : Maintaining detailed documentation of the design process, including specifications, design decisions, and verification results Product Support : Pre and Post Production Stages, Support for RMA Required Skills & Experience - Min 8+ years of experience in System Architecture for ARM based MCU product development - Min 8+ years of experience in RTL Design, Coding and RTL Integration, - Strong design and debugging skills. - Experience in handling Verification Teams. Verification environment Development , Static and Dynamic Verification, Test Management. (UPF, GLN, Test Mode) - Experience with industry-standard EDA tools for LINT, CDC, SDC validation, and power analysis preferably Synopsis EDA. - Exposure to Backend and Analog processes. - Ability to collaborate effectively with backend teams (PD, DFT, and STA) to achieve timing and power closure. - Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience - Min 1+ years of Project Management (Waterfall and Agile – Hybrid Methodology). - Continuous Improvement. - Knowledge of industry standards and best practices in semiconductor front-end design. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field

Generic Job Description (not Job Level specific): The Design Methodologies and Tools Engineer / Architect develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assesses architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Bangalore Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP FI S/4HANA Accounting Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will be involved in designing, building, and configuring applications to meet business process and application requirements. Your typical day will revolve around creating innovative solutions to address specific business needs and ensuring seamless application functionality. Roles & Responsibilities:- Liaising with clients to gather necessary requirements and resolve GST-related queries.- Configuring and maintaining GST settings in SAP, including TDS, E-invoice, and other tax-related modules.- Configuring and Testing of GST returns (Document compliance Reporting), To ensure compliance with GST laws and regulations.- Proficient in implementing and handeling third party integration- Join Cluster Tax team, focusing on localization and deployment- he/she will need to have experience in/with SAP tax reporting or tax determination- he/she will support tax localization requirements during the full project lifecycle.- he/she will review build demos and test results against design/- he/she will support country users in organizational change activities and ensure country users know & act on their responsibilities- he/she will perform cutover and hypercare activities- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Lead the team in implementing best practices for SAP FI S/4HANA Accounting- Conduct regular code reviews and ensure adherence to coding standards- Stay updated with the latest trends in SAP FI S/4HANA Accounting and provide training to team members Professional & Technical Skills: - Strong knowledge of GST laws and regulations.- Proficiency in SAP FICO with experience in end-to-end implementations.- SAP Experience in baseline configuration for GST India in SAP. Experience in SAP FI, MM, and SD.- Must To Have Skills: Proficiency in SAP FI S/4HANA Accounting- Strong understanding of financial accounting principles- Experience in configuring and customizing SAP FI modules- Knowledge of integration with other SAP modules- Hands-on experience in SAP implementation projects- SAP Tax Accounting- SAP S/4HANA Finance- SAP Tax reporting- SAP Tax determination- SAP ARC/DRC is a plus Additional Information:- The candidate should have a minimum of 7.5 years of experience in SAP FI S/4HANA Accounting- This position is based at our Hyderabad office- A 15 years full-time education is required Qualification 15 years full time education

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, data center, and networking applications. What You Can Expect As a Senior Staff Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 9+ years of experience running an industry standard EDA tool for PnR & signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Chennai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

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Primary & Mandatory Skill: Python, Docker/Kubernetes Level: SA Client Round (Yes/ No): No Location Constraint if any : No Shift timing: 2-11pm JD: Good hands in Python scripting Experience in Docker & Kubernetes

SMTS SILICON DESIGN ENGINEER (AECG ASIC Physical Design Implementation) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 14years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 10years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SENIOR SILICON DESIGN ENGINEER ASIC Physical Design Engineer THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Provide technical support to other teams PREFERRED EXPERIENCE: 5years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

**Job Summary:** We are looking for an experienced and results-driven IC Physical Design Engineer with 5+ years of hands-on experience in digital backend implementation of complex SoCs or ASICs. In this role, you will lead or contribute significantly to block-level and full-chip physical design, timing closure, and sign-off processes in advanced technology nodes. You will work cross-functionally with RTL, DFT, verification, and packaging teams to deliver high-quality silicon on aggressive schedules. **Key Responsibilities:** + Lead physical implementation of blocks and/or full chip through all stages: floorplanning, power planning, placement, CTS, routing, and sign-off. + Drive timing closure using static timing analysis (STA) and optimization techniques for PPA (Power, Performance, Area). + Own physical verification (LVS, DRC, Antenna, ERC) and ECO implementation. + Perform IR/EM analysis, noise checks, and low power verification (UPF/CPF-based). + Interface with RTL, DFT, and verification teams to resolve cross-functional issues and ensure successful tape-out. + Guide junior engineers and review their work to maintain high quality and consistency. + Develop automation scripts to streamline physical design tasks using TCL, Python, or Perl. Collaborate with CAD/Methodology teams to enhance \#LI-RT1 **More details about our company benefits can be found here:** https: / / www.onsemi.com / careers / career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

Primary/ Mandatory skills : Extensive experience in “Chef IT Automation” Secondary skills : Good knowledge and experience in DevOps Level: SA RR : Maintain a consistent terraform script when compared to existing cloud resources Chef version update: version 14 to version 18 Crowdstrike, Qualys and Splunk integration for Ecommerce workloads Packer AMI creation for Windows Core and CentOS Stream 9 Terraform version update Collaborate with DB team for “CentOS version + DB version” update project Test every change made. Work with DevOps, SRE and development teams for testing. Document and publish the changes, and projects undertaken. Client Round (Yes/ No): Yes Location Constraint if any : No Constraints Shift timing: IST 1330Hrs – 2330Hrs

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure correct IP and pad-ring integration in block and flat designs. Mentor junior PD/PV team members and oversee their tasks. You will be reporting to ASIC Design Director. What Youll Need: Minimum 12+ Years of experience in ASIC/ SoC Physical Design. Skills - have working experience in advanced FinFET node designs. Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must. Education - B. Tech /M. Tech in Electronics Engineering. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.