ASIC Design Lead, Machine Learning, Silicon

As a Senior RTL Design Engineer at Google, you will play a crucial role in developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind globally beloved products. Your expertise will be instrumental in shaping the next generation of hardware experiences, focusing on delivering unmatched performance, efficiency, and integration. Key Responsibilities: - Manage a team of RTL engineers, overseeing the design of complex machine learning compute IPs by fully comprehending architecture specifications and collaborating with software and architecture engineers to identify crucial design requirements. - Collaborate with Verification and Silicon Validation teams to ensure the functionality of the design. - Offer insights on synthesis, timing closure, and physical design of digital blocks. - Guide and motivate the team to meet deadlines and achieve exceptional Power Performance Area (PPA) benchmarks for IPs integrated into various SoCs. - Coordinate with SoC Design and other cross-functional implementation teams to ensure successful implementation of IP design through downstream domains up to tape-out. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. - 10 years of experience in RTL design. - Experience in leading a team through the full development cycle of SoC subsystems, such as Neural Processing Units, GPU, DSP, or processors, from conception to production. - Cross-functional collaboration experience with Software, Architecture, Design Verification, and SoC integration teams. Preferred Qualifications: - Master's degree or PhD in Computer Science, Electrical Engineering, or a related field. - Engineering experience spanning across architecture, micro-architecture, design verification, implementation, emulation, and silicon bring-up. - Familiarity with high-performance compute IPs like GPUs, DSPs, or Neural Processing Units.,