439 Physical Design Jobs - Page 9

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

- Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 10 to 15 years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design - Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements. - Follow agile project leadership principles. Work with the team on estimation and execution plan. - Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary. Preferred technical and professional experience Bachelors / Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

We have roles in the digital and analog domains wherein you will be:Working towards definition, design, verification, and documentation for SoC(System on a Chip) developmentDetermining architecture design, logic design, and system simulationPerforming all aspects of SoC design flow-from high-level design tosynthesis, place and route, timing, and power-to create a design databasethat is ready for manufacturingTranslating SoC requirements to analog circuit specifications, architectingand designing analog IPs: ADC/DAC, LDOs, PLLs, temperature sensors, etc.Designing innovative analog and mixed signal circuits and contributing todelivering analog IPs in advanced Intel process nodesCollaborating with the SoC team for IP integration, silicon tests, etc.Developing and supporting OFT strategy and implementationCollaborating with the bench validation team for silicon validation,debugging, etc.Hardware Engineering Intern Qualifications: QualificationsAny candidate for a temporary full-time internship position must be:Currently enrolled in a relevant Bachelor's/Master's degree from a reputedacademic instituteAvailable for a 1-year internship (course completion by June/July 2026)Willing to ramp-up quickly on required areas like Microelectronics, RTL,verification/validation, structural design/physical design, analog, and so on Job Type: Student / Intern

Expertise in logic synthesis, conformal, static timing analysis and Place and Route (PnR) Hands on experience in all aspects of the chip development process Experience in creating or improving low power synthesis methodologies Experience with scripting languages like Perl, Tcl or Python Floorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block level RTL logic design or implementation experience on multi-million gate ASICs will be a plus Strong communication skills to effectively communicate across all internal groups Description: As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC design and implementation. Responsible for activities like Synthesis, LEC, Conformal, P&R etc. You will be working closely on methodology for improving synthesis QOR. Responsible for floor planning, placement and routing at block level. Will need to work closely with other engineers that are members of the RTL, STA and Physical Design teams. Education & Experience: BS or MS in EE, EECS, or CS is required 4+ years relevant work experience

Building, implementing and supporting SSRS, SSIS and Power BI solutions Responsible for logical design, physical design, implementation, testing and deployment of BI project. Understand complex business problems and implement product features that are secure, scalable, robust and easy to implement and maintain. Take full ownership of product features to implement, provide bug fixes and write tests and tooling for those features to ensure they work we'll at cloud scale. Take pride of ownership in features that are used by users of Top 100 Global enterprises. Out of the box thinking for optimizing work and providing best in class Solution. Self-Motivated who can understand the requirements with limited guidance and develop product features, and has the ability understand the impact of the feature change on the overall product. Building, implementing and supporting SSRS, SSIS and Power BI solutions Responsible for logical design, physical design, implementation, testing and deployment of BI project. Understand complex business problems and implement product features that are secure, scalable, robust and easy to implement and maintain. Take full ownership of product features to implement, provide bug fixes and write tests and tooling for those features to ensure they work we'll at cloud scale. Take pride of ownership in features that are used by users of Top 100 Global enterprises. Out of the box thinking for optimizing work and providing best in class Solution. Self-Motivated who can understand the requirements with limited guidance and develop product features, and has the ability understand the impact of the feature change on the overall product. Should have 2+ years of experience in SSRS, SSIS and Power BI. Experience with the Microsoft BI stack, Azure and exposure to SQL Server database is a MUST. Should be hands on SSRS with exposure to Relational Database, Strong SQL Language. Should have experience in Performance tuning of reporting queries, Writing Tablix/matrix SSRS reports. Should have Power BI development and deployment knowledge Should have worked on SSIS Development and architecture design for complex systems. Should have experience in end-to-end implementation of Business Intelligence (BI) projects, especially in scorecards, KPIs, reports & dashboards, SSIS Packages. Should have excellent verbal and written communication skill. Should have 2+ years of experience in SSRS, SSIS and Power BI. Experience with the Microsoft BI stack, Azure and exposure to SQL Server database is a MUST. Should be hands on SSRS with exposure to Relational Database, Strong SQL Language. Should have experience in Performance tuning of reporting queries, Writing Tablix/matrix SSRS reports. Should have Power BI development and deployment knowledge Should have worked on SSIS Development and architecture design for complex systems. Should have experience in end-to-end implementation of Business Intelligence (BI) projects, especially in scorecards, KPIs, reports & dashboards, SSIS Packages. Should have excellent verbal and written communication skill.

Engineer / Sr Engineer (Linux BSP), eInfochips, 4 - 10 years, Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore - ACHNET Are you sure you want to cancel? Are you sure you want to cancel this Profile? You can always come back later Edit Profile The first thing people see You do not have permission to access the Talent Management menu. This section is restricted to Admins and Editors only. If you believe you should have access, please contact your administrator for assistance. YOUR BROWSER IS NOT SUPPORTED To view this experience, please upgade to the latest one of these browsers Engineer / Sr Engineer (Linux Bsp) DESCRIPTION Job Description, Role Responsibilities POSITION TITLE: EXPERIENCE: Role: LOCATION: Engineer / Sr Engineer (Linux BSP) 4-10 Years Linux BSP Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore Company Profile eInfochips An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and Azure. Our work culture is built over years of experience in providing innovative solutions to our clients and our indomitable spirit to excel in all aspects of our engagement. We believe that our success lies upon the skills and quality of our people we work with. Silicon engineering services: ASIC / FPGA Design Development, Design Verification Validation, Physical Design DFT Embedded systems engineering services: Hardware Design, System Software, System Verification Validation, Multimedia Software engineering services: Cloud Enablement, IoT Mobility, Application Software, QA and Test Automation, BI and Data Visualization Extended services: New Product Development, Lifecycle Management, Product Sustenance IPs: DevOps for IoT, IoT Gateway Framework, IoT Device Lifecycle Management, Video Management Software, Reusable Camera Framework, Test Automation Framework, Reference Designs EVMs, Verification IPs, OptiX Physical Design Framework About Arrow Electronics Arrow Electronics (www.arrow.com) guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2021 sales of $34.48 billion, we develop technology solutions that improve business and daily life. Our strategic direction of guiding innovation forward is expressed as Five Years Out (Five Years Out | Arrow Electronics), a way of thinking about the tangible future to bridge the gap between what s possible and the practical technologies to make it happen. www.einfochips.com Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies. In addition, the right candidate will: Incumbent works under general supervision Incumbent has substantial experience to resolve problems and concepts Incumbent can work on complex concepts and implementation www.einfochips.com Be a highly energetic self-starter Be an open and excellent communicator Have exceptional interpersonal skills Be a consummate team player Interface well with Client Engineer Team members and other Business Units of eInfochips Finally, this individual must have an uncompromising level of personal integrity. Education A Graduate degree in Electronics and communication/Information Technology/Computer-Science is required. A Masters technical degree is highly desirable.

Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon debug. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Apply to this job Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. EDA Infrastructure Engineers are individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, EDA Infrastructure Responsibilities Front End implementation flow development and support Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance Work with internal infrastructure team on adapting Meta infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting RTL2GDS flow development and support Physical Design implementation flow development and support Minimum Qualifications Knowledge of front-end and back-end ASIC tools and flows Experience with RTL design using SystemVerilog or other HDL 8+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support Experience with developing and supporting solutions for ASIC design environment and infrastructure Experience with communicating across functional internal teams and with vendors Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications Experience setting up EDA infrastructure from scratch User experience and customer oriented solutions About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon debug. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 3 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred experience: Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M. Tech/ B. Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

: We are looking for a highly skilled and experienced Physical Design Lead to join our VLSI team. The ideal candidate will have a strong background in physical design and a deep understanding of the VLSI design flow. This role involves leading a team of engineers and working closely with cross-functional teams to ensure the successful implementation and optimization of physical designs. Key Responsibilities: Lead the physical design team in the implementation of complex digital designs, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Collaborate with RTL design, verification, and DFT teams to ensure design quality and robustness. Develop and implement physical design methodologies and best practices to improve design efficiency and quality. Perform static timing analysis, power analysis, and signal integrity analysis to ensure design performance and reliability. Interface with foundry and EDA tool vendors to resolve design issues and improve design flow. Mentor and coach junior engineers, providing technical guidance and support. Participate in design reviews and provide feedback to improve design quality and efficiency. Qualifications Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. Extensive experience in physical design, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk. Strong understanding of static timing analysis, power analysis, and signal integrity analysis. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate clearly with cross-functional teams. Experience in mentoring and coaching junior engineers is a plus. Company Description About Renesas: Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Role: Physical Design Engineer Experience Required: 5-15 Years Work location: Noida Minimum Experience required is 5 Years in Physical Design Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry. Sound expertise in Tcl, Perl, and Shell scripting. Technically sound & good team player Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence Innovus / Encounter) is a must. Experience with latest technology (28nm,16nm,7 nm) Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Urgent Hiring VLSI Physical Design / STA / EMIR Engineers (Immediate Joiners Only) | Pune Location Location: Pune Notice Period: Only Immediate Joiners Hiring Duration: Till 3rd Week of June Mode: Full-time Opportunity 1. Physical Design Engineer Experience: 4 to 6 Years Key Responsibilities: Full RTL-to-GDSII flow execution including floorplanning, power planning, placement, CTS, routing, DRC/LVS closure. Work on advanced technology nodes (7nm/5nm and below). Experience in hierarchical and flat implementation. Ownership of block-level PnR, timing closure, IR/EM, and physical verification. Interfacing with cross-functional teams RTL, DFT, PD, and verification teams. Required Skills: Strong expertise in tools like ICC2, Innovus, PrimeTime, RedHawk. Scripting in TCL/Perl/Shell to automate design tasks. Understanding of timing, noise, congestion, and power trade-offs. Good analytical and debugging skills. 2. STA Engineer Experience: 6 to 12 Years Key Responsibilities: Responsible for full-chip/block-level Static Timing Analysis and sign-off. Support physical design and timing convergence teams. Create and validate timing constraints (SDC), analyze paths, and suggest optimizations. Perform ECO implementation and validation. Sign-off checks including noise, DRC, SI, IR, and leakage power. Required Skills: Expert in using Synopsys PrimeTime (or equivalent STA tool). Deep understanding of timing concepts – setup, hold, skew, clock uncertainty, etc. Proficiency in scripting (TCL/Perl). Experience with multi-corner, multi-mode (MCMM) STA. Strong debugging and closure experience across multiple tapeouts. 3. EMIR Engineer (IR/EM Analysis) Experience: 5 to 9 Years Key Responsibilities: Perform IR drop and Electromigration (EM) analysis using tools like RedHawk, Voltus. Define EM/IR methodologies and flows. Collaborate with design teams to improve power grid design and robustness. Ensure sign-off quality results for high-performance SoCs. Create automated checks and regression flows. Required Skills: Strong knowledge of power integrity issues and reliability concerns at advanced nodes. Familiarity with power grid design, decap planning, and current estimation. Hands-on experience with EMIR tools (Ansys RedHawk, Cadence Voltus). Good knowledge of PnR flow and integration with IR/EM requirements. Qualifications for All Roles: B.E/B.Tech or M.E/M.Tech in Electronics/VLSI/EEE. Proven tapeout experience in complex SoCs. Excellent communication and problem-solving skills. Why Join Us? Work with cutting-edge technology on advanced nodes. Collaborative team environment with domain experts. High-impact, visible roles with leading semiconductor customers. Apply Now – Immediate joiners preferred. Note: This requirement is open only till the 3rd week of June .

We are looking for an experienced Physical Design Lead with expertise in Netlist2GDSII implementation , including floor planning , power grid design , CTS , STA , and physical verification . The ideal candidate will have proficiency in Cadence and Synopsys tools and experience with 16nm and below technologies , along with a strong background in SoC integration and low-power/high-speed designs . Leadership in managing teams, handling complex designs, and proficiency in Tcl/Tk/Perl programming is essential, along with excellent communication and customer interaction. Roles & Responsibilities: You should have 10+ years of hands-on experience with Netlist2GDSII implementation , including key processes such as floor planning , power grid design , placement , clock tree synthesis (CTS) , routing , static timing analysis (STA) , power integrity analysis , physical verification , and chip finishing . Expertise in physical design methodologies with experience working on sub-micron technologies (16nm and below). Proficiency with PnR tools from Cadence and Synopsys ( Innovus , ICC2 ). Strong background in Static Timing Analysis (PrimeTime SI) , EM/IR drop analysis (PT-PX, Redhawk) , and physical verification (Calibre) . Practical knowledge in applying methodologies and physical design tools, with experience in flow automation and process improvements . Hands-on experience in SoC integration , low-power and high-speed designs , and advanced physical verification techniques . Proven success in handling designs with >5M instance count and 1.5GHz frequency . Expertise in programming (Tcl/Tk/Perl) to automate design processes and improve efficiency. Excellent customer interaction , communication , and teamwork skills, ensuring smooth collaboration with internal teams and clients.

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. As a Physical Design Engineer, you will: Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level. Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals. Drive and Develop Physical Design Tool features, Flow automations and Methodology enhancements in order to achieve PPA goals, low power requirements. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams BS in EE/CS Minimum 5years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation. MS or PhD degree in Computer Engineering/Electrical Engineering or related field Excellent communication and analytical skills Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Minimum 7years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain Thorough knowledge of device physics, custom/semi-custom implementation techniques Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc. Experience in extraction of design parameters, QOR metrics, and analyzing trends Experience with DFT & DFM flows Ability to provide mentorship, guidance to junior engineers and be a very effective team player

Minimum Experience required is 4 Years in Physical Design Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry.

Experience with floor planning, automatic placement and routing, timing/physical fixes Innovus / Soc Encounter @ Cadence - ICC2/IC Compiler@Synopsys [Preferred] -to strategies for improvement - Experience with layout physical verification Caliber

Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years What would you do? "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for? " Agility for quick learning Ability to work well in a team Process-orientation Written and verbal communication Network fundamentals Understanding all the networking devicesRouters, switches, etc. IP connectivity, access, addressing, and services Network security fundamentals Installation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business Networks Excellent Communication Problem Solving Skills Flexibility Teamwork Experience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: " In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shifts Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity Provide 24/7/365 monitoring of ticket queue, phones, and IRC channel Manage network events such as: Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updates Link Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the output Manage client s optical network, manage alarms and faults in a multi-vendor environment, and Tracking of all work in ticketing system network interconnects with internal and external network operators Track and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providers Manage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary. Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacement Read/Parse vendor notifications and translate to Clients Production Change Request (PCR s) Look up affected circuits to include them in change request Escalate any emergency change requests for immediate review and scheduling Navigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation