Physical Verification

In a fast-paced leading-edge design environment with endless possibilities of innovation and learning, you will be responsible for ensuring flawless execution in specific areas of SoC level Physical Design such as Physical Verification, Tapeout, ESD Verification, and Pre-emptive Quality audits of incoming designs. This is a great opportunity to join a team of talented individuals working on state-of-the-art complex SoC Designs as part of Intel Foundry Design Services and Reference Design Development teams. - Integration and generation of layout and netlist views of different levels of hierarchy up to SoC. - Layout verification and signoff for IP blocks, APR partition, and SoC levels of hierarchy. - Develop Tcl and Perl script automations to efficiently implement layout edits in APR designs. - Develop plans and implement the audit of incoming layouts, thereby setting minimum acceptable criteria. - Execute Structural Design health checks that can have a bearing on layout quality. - Partner with design teams to build SoC DB that meets foundry requirements for Tape-outs. - Provide timely feedback to design teams on layout quality throughout the design phase of a project. - Liaison with PDK, Tools, flow and Methodology teams along with other stakeholders to pre-empt issues and to be abreast of the latest changes in foundry rules. - Effectively communicate with large numbers of design and layout engineers providing high-quality documentation and presentations. - Bachelors or Masters in Electrical or Electronics Engineering. - 2+ years of experience in Physical Design and Verification or Design Implementation or Design automation. - Experience with APR or Custom layout implementation tools or Custom / APR tool flow methodologies. - Should have experience in either IP or SoC level layout design or backend sign-off process. - Good understanding of Layout Signoff requirements such as DRC, LVS, DFM, and Reliability checks. - Experience with TCL or Perl programming.,