Physical Verification

Job Title: Physical Verification Engineer

Location: Hyderabad

Work Type: Full-time | Hybrid

Job Summary

Physical verification engineer for

SOC/blocks

Key Responsibilities

• Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes.

• Address critical design and execution challenges associated with physical verification and sign-off.

• Have a comprehensive understanding of physical verification and sign-off workflows and methodologies.

• Partner with PNR engineers to achieve sign- off at various stages of the design process.

Qualifications and Skills

Proficient in physical verification for SoC/full-chip andblock-level processes, including DRC, LVS, ERC/PERC,

DFM, OPC, and tapeout.

• Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2.

• Skilled in troubleshooting LVS issues at the chip level,particularly with complex analog-mixed signal IPs.

• Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and

substrate isolation.

• Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip

components.

• Capable of developing sign-off methodologies/flows and providing support to larger teams.

• Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset.

• Experience in floorplanning is a plus.