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0.0 years
0 Lacs
bengaluru, karnataka, india
On-site
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...
Posted 1 day ago
0.0 years
0 Lacs
india
On-site
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...
Posted 1 day ago
3.0 - 7.0 years
0 Lacs
hyderabad, telangana
On-site
In this role, you will have complete ownership of individual circuit blocks in a DDR PHY design within cutting edge process technology nodes. Your responsibilities will include circuit design, layout quality, electrical and timing analysis, and reliability checks. Additionally, you will interface with cross-functional teams such as RTL, Verification, and Physical Design. Preferred Experience: - Strong hands-on experience in DDR circuit designs in the latest process technology nodes - Good technical knowledge of power-performance trade-offs in high-speed DDR and/or SerDes architectures - Direct experience in all phases of design analysis including functional, static timing, and electrical sig...
Posted 1 month ago
0.0 years
0 Lacs
hyderabad, telangana, india
On-site
Key Responsibilities Complete ownership of individual circuit blocks in a DDR PHY design in cutting edge process technology nodes Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks Interface with cross-functional teams like RTL, Verification and Physical Design Preferred Experience Strong hands-on experience in DDR circuit designs in latest process technology nodes. Good technical knowledge of power-performance trade-offs in high-speed DDR and/or SerDes architectures Direct experience in all phases of design analysis including functional, static timing and electrical sign-off Strong understanding of the impact of variation on design perform...
Posted 1 month ago
2.0 - 6.0 years
0 Lacs
karnataka
On-site
In a fast-paced leading-edge design environment with endless possibilities of innovation and learning, you will be responsible for ensuring flawless execution in specific areas of SoC level Physical Design such as Physical Verification, Tapeout, ESD Verification, and Pre-emptive Quality audits of incoming designs. This is a great opportunity to join a team of talented individuals working on state-of-the-art complex SoC Designs as part of Intel Foundry Design Services and Reference Design Development teams. - Integration and generation of layout and netlist views of different levels of hierarchy up to SoC. - Layout verification and signoff for IP blocks, APR partition, and SoC levels of hiera...
Posted 1 month ago
4.0 - 8.0 years
0 Lacs
karnataka
On-site
As a Physical Design Engineer at UST, you will be responsible for the following: - Expected to be very good in Basic Fundamentals of C-MOS technology - Able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred) - Hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. - Proficient in floor planning, placement optimizations, clock tree synthesis (CTS), and routing - Experienced in block/top level signoff Static Timing Analysis (STA), physical verification (DRC/LVS/ERC/antenna) checks, and other reliability checks (IR/EM/Xtalk) - Expertise in industry standard EDA t...
Posted 2 months ago
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