Physical Design Engineer

VantaHire

7 - 15 years

30 - 75 Lacs

Pune Maharashtra India

Posted:10 hours ago| Platform:

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Skills Required

design drive synthesis cadence synopsys fusion compiler timing analysis drc lvs dft packaging power signal integrity technology debugging management verification

Work Mode

On-site

Job Type

Full Time

Job Description

Job Title:

Physical Design Engineer

Domain: Semiconductor | VLSI | Chip Design
Experience: 7 to 15 Years
Location: Bangalore / Hyderabad / Cochin / Pune
Budget: ₹30 LPA to ₹75 LPA
Work Mode: 5 Days Office

Key Responsibilities

End-to-end ownership of chip-level and block-level floor planning.
Drive partitioning, placement, clock tree synthesis (CTS), and routing.
Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation.
Perform timing analysis, DRC/LVS closure, and physical verification.
Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams.

Key Skills Required

Strong experience in chip-level and block-level physical design.
Hands-on expertise with Innovus and/or Fusion Compiler.
Solid understanding of timing, power, signal integrity, and physical verification.
Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus.
Excellent problem-solving and debugging skills.

Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

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