Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

About Company Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. We’re Hiring – DFT (Design for Test) Engineer Locations: Bangalore | Hyderabad | Cochin | Pune Experience: 7 to 12 Years Qualification: Bachelor’s in Computer Science / Electronics / Electrical Engineering Key Responsibilities Collaborate with ASIC design teams to ensure DFT rules and coverage are met Generate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teams Support post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-up Enhance and maintain scripting for DFT flows Preferred Experience & Skills Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG – TestKompress MBIST – MentorETVerify Simulation – VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Qualifications Bachelor’s degree in Computer Science, Electronics, or Electrical Engineering Minimum of 7 years of relevant experience in DFT Strong analytical and troubleshooting skills Ability to work independently and as part of a team Excellent verbal and written communication skills Experience with industry-standard tools and methodologies Benefits and Perks Competitive Salary Good work culture Skills: memory test,dft,failure analysis,atpg,communication,scripting,silicon validation,mbist

About The Role We are seeking a highly motivated and dynamic Account Executive to join our team in Mumbai. The ideal candidate will have a strong background in enterprise sales , particularly in selling SaaS products such as LMS , CRM , or HRMS platforms. This is an exciting opportunity to work with cutting-edge solutions, engage with enterprise clients, and contribute to business growth. Key Responsibilities Identify and pursue new business opportunities in the enterprise segment Pitch SaaS solutions (LMS, CRM, HRMS, etc.) to potential clients Own the entire sales cycle – from lead generation to closing deals Develop and maintain long-term relationships with clients Meet and exceed revenue targets and performance KPIs Collaborate with internal teams for seamless client onboarding and support Conduct product demonstrations and business presentations as required Maintain accurate records of sales activities and pipeline management Requirements 2 to 4 years of proven experience in SaaS sales, Enterprise B2B sales, or related domains Prior experience in selling LMS, CRM, HRMS, or other SaaS platforms is mandatory Excellent communication, negotiation, and presentation skills Ability to work independently and manage time efficiently Willingness to travel for client meetings when required Bachelor's degree in Business, Marketing, or related field Skills: saas,lms,communication,saas sales,time management,enterprise sales,crm,presentation,hrms,negotiation,enterprise

About Company Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. We’re Hiring – DFT (Design for Test) Engineer Locations: Bangalore | Hyderabad | Cochin | Pune Experience: 7 to 12 Years Qualification: Bachelor’s in Computer Science / Electronics / Electrical Engineering Key Responsibilities Collaborate with ASIC design teams to ensure DFT rules and coverage are met Generate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teams Support post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-up Enhance and maintain scripting for DFT flows Preferred Experience & Skills Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG – TestKompress MBIST – MentorETVerify Simulation – VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Qualifications Bachelor’s degree in Computer Science, Electronics, or Electrical Engineering Minimum of 7 years of relevant experience in DFT Strong analytical and troubleshooting skills Ability to work independently and as part of a team Excellent verbal and written communication skills Experience with industry-standard tools and methodologies Benefits and Perks Competitive Salary Good work culture Skills: memory test,dft,failure analysis,atpg,communication,scripting,silicon validation,mbist

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

About Company Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. We’re Hiring – DFT (Design for Test) Engineer Locations: Bangalore | Hyderabad | Cochin | Pune Experience: 7 to 12 Years Qualification: Bachelor’s in Computer Science / Electronics / Electrical Engineering Key Responsibilities Collaborate with ASIC design teams to ensure DFT rules and coverage are met Generate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teams Support post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-up Enhance and maintain scripting for DFT flows Preferred Experience & Skills Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG – TestKompress MBIST – MentorETVerify Simulation – VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Qualifications Bachelor’s degree in Computer Science, Electronics, or Electrical Engineering Minimum of 7 years of relevant experience in DFT Strong analytical and troubleshooting skills Ability to work independently and as part of a team Excellent verbal and written communication skills Experience with industry-standard tools and methodologies Benefits and Perks Competitive Salary Good work culture Skills: memory test,dft,failure analysis,atpg,communication,scripting,silicon validation,mbist