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Mirafra
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Physical Design Engineer

Physical Design Engineer

3 - 8 years

|

6 - 11 Lacs

noida hyderabad bengaluru

Posted:4 hours ago| Platform:

Apply

Skills Required

physical design floorplan tk perl tcl synthesis sta primetime device drivers lvs innovus timing analysis cadence physical verification routing floor planning signal integrity rtos timing closure drc genus pnr linux placement

Work Mode

Work from Office

Job Type

Full Time

Job Description

Skills/Experience:

Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler.
Proficient in top-down floorplan and Power Grid methodologies.
Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff.
Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as
Genus, Innovus, Quantus, Tempus, PVS, Voltus
.
Automation and programming-minded, coding experience in Tcl/Tk/Perl.

Education Qualification:

B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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