Physical Design Engineer

10 years

0 Lacs

Posted:1 day ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Key Responsibilities:

  • Drive block-level and/or full-chip physical design from RTL to GDSII.
  • Floorplanning, placement, clock tree synthesis (CTS), and routing.
  • Work on static timing analysis (STA) and timing closure.
  • Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM).
  • Collaborate with RTL, DFT, synthesis, verification, and packaging teams.
  • Ownership of PPA (Power, Performance, Area) targets and meeting timing goals.
  • Participate in multiple tape-outs and manage block-level signoff closure.
  • Automate and optimize flows using Tcl, Perl, Python, or shell scripting.
  • Keep up-to-date with the latest EDA tools and technology trends.

Required Skills & Experience:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field.
  • 4–10 years of experience in physical design with successful tape-outs.
  • Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.).
  • Deep understanding of digital design concepts, timing, and power trade-offs.
  • Hands-on experience in advanced technology nodes (16nm and below preferred).
  • Experience with scripting languages (Tcl, Python, Perl, Shell).
  • Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF).
  • Knowledge of signal and power integrity issues (IR/EM) is a plus.

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