242 Mixed Signal Jobs - Page 2

Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Master s degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical background in digital design, verification, and silicon validation with understanding of the SD, UHS and SD-Express standards. Excellent cross-functional leadership and communication skills. Ability to manage technical risks and drive execution in a fast-paced environment. Passion for innovation and delivering high-quality, scalable solutions. Preferred Qualifications: Proficiency with EDA tools and methodologies for ASIC development. Familiarity with industry standards and best practices in semiconductor design. Expertise in low-power design techniques and high-speed interfaces.

We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 9-14 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 9-14 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor s or Master s degree in Electronics or Electrical Engineering

Having 5 - 8 + years experience in the Embedded hardware design. Experience in High speed boards, Mixed Signal board based on Microprocessor, Microcontroller (8/16/32), FPGA, CPLD. Involved in the complete design life cycle from Project Proposal to delivery. Exposure to Product Life Cycle in Design and Development of System Level. Expertise in component selection based on the project requirement, Schematics Design creation, design review, layout guidelines for high speed design, Gerber generation review, PCB stack up analysis and communicated with PCB fabricator to solve the EQ. Experienced in Digital/Analog circuit design, circuit Simulation, high speed design, high speed layout review. Involved working with communication protocols SPI, I2C, UART, PCI, LVDS, MIPI-DSI, DDR4 interface. Involved in preparing documents like Design HLD, Test cases for testing the board. Involved and Prepared inputs documents for thermal analysis, PI, SI. Experienced in reviewing PI, SI reports. Handling the diverse testing instruments like oscilloscope, logic analyzer, functional generator and analyzer. Executed Customer Demo and PoC. Experience in prototype products development, test strategies, test case generation, BOM generation prepared test document for EMI AND EMC Test. Supported other Team Members/Teams by sharing knowledge through sessions and provided Technical Support across the organization.

Experience with signal chain optimization is highly desired Key Duties & Responsibilites + Must have a working knowledge of Cadence Circuit design tools + Analytical approach to problem solving is required CMOS designs provide challenging learning opportunities where performance, power and reliability are all pushed to the limit while maintaining product execution schedule + Drive development and verification of state-of-the-art analog blocks and mixed signal CMOS designs which can be reused across different market segments + Participate in analog circuit requirements discussions, technical issues and other design aspects to arrive at agreed upon product specifications + Build/develop circuits based on an IP specification, drive the layout design and final IP characterization + Execute state-of-the-art analog designs while following the best design practices with on time quality design releases + Propose innovative and creative solutions where necessary to meet customer & product needs + Work diligently with the given requirements to accomplish project goals and meet schedule requirements + Debug of complex integrated circuit problems in the laboratory Collaborate in debug efforts as needed + Perform bench characterization and support application engineering bench evaluation efforts + Analyze design aspects related to DFT and collaborate with other team members to develop DFT strategy for block designs +

This position offers a great opportunity to work on industry leading semiconductor devices, targeted for broad applications in Automotive and Industrial markets In this role, you ll be a member of New Product Development team, tasked with supporting product lines and business P&Ls on new product development activities, including defining Analog/Digital DfT and test strategies, developing low-cost test solutions for complex Analog, Mixed Signal, and Digital roadmap products on ATE platforms, and productizing ICs in-line with business goals and growth projections Knowledge and experience with software development utilizing C++ / C / Python / JAVA is necessary Candidate should know ATE platform architecture and programming languages to develop low level ATE code for Analog / Mixed Signal blocks End goal is to design and productize deep Analog and Mixed Signal test automated solutions, enabling organization benchmarks in quality, efficient code, and test-cost goals onsemi*(Nasdaq: ON) is driving disruptive innovations to help build a better future With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure

This position offers a great opportunity to work on industry leading semiconductor devices, targeted for broad applications in Automotive and Industrial markets In this role, you ll be a member of New Product Development team, tasked with supporting product lines and business P&Ls on new product development activities, including defining Analog/Digital DfT and test strategies, developing low-cost test solutions for complex Analog, Mixed Signal, and Digital roadmap products on ATE platforms, and productizing ICs in-line with business goals and growth projections Knowledge and experience with software development utilizing C++ / C / Python / JAVA is necessary Candidate should know ATE platform architecture and programming languages to develop low level ATE code for Analog / Mixed Signal blocks

Job Description: The Mixed Signal Development Group is responsible for delivering analog and mixed-signal IP to divisions within Microchip. We work with leading edge CMOS processes to produce analog integrated circuits for wireline applications. From T1/E1 to 112Gb/s SERDES, we enable technology that allows Microchip s products to interface to the outside world. As a member of the Mixed-Signal Development Group, the candidate will be supervised by a team leader/manager, and be engaged in the design of PLLs, high speed SERDES, integrated filters, ADCs, DACs, and other analog building blocks. Responsibilities: Lead and support Mixed-Signal IP from conception through post-tapeout phase, including lab testing, customer bring-up and debug Interface and communicate with internal business units on IP support and technical topics Lead analog design developments Work with 3rd party analog IP vendors for integration into products Design and architect CMOS analog and mixed-signal integrated circuits Ownership of circuit and system specifications Requirements/Qualifications: Masters Degree or PhD in Analog, Mixed-Signal or RF IC design strongly preferred 15+ years of industry experience in the area of mixed-signal CMOS circuit design Experience in leading/managing a analog team is a prerequisite. Experience with high-speed SERDES/Clocking circuits is an asset Knowledge of layout issues Experience with circuit simulators (HSPICE, Spectre, etc) Experience with Cadence Design Environment is an asset Strong written and oral communication skills Ability to quickly ramp on new projects Travel Time: 0% - 25%

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans in alignment with project requirements, specifications, and design schematics. As a Layout Engineer, you will utilize your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Your responsibilities will include conducting analyses, tests, and verifications using various tools and techniques to identify and troubleshoot issues, while staying updated on new verification methods. Collaboration with multiple internal and external stakeholders is essential to align on projects, provide updates, and resolve any issues that may arise. The ideal candidate for this role will hold a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field, along with a minimum of 2 years of experience in designing custom layouts in a relevant domain such as analog, mixed signal, RF, or digital design. Alternatively, an Associate's degree with 4+ years of relevant experience or a High School diploma with 6+ years of relevant experience will also be considered. Additionally, candidates should have at least 2 years of hands-on experience using layout design and verification tools like Cadence, LVS, and rmap. Candidates with a solid experience ranging from 8 to 12 years in developing high-speed IO/ESD/Analog layout design are preferred. Expertise in working on FinFet layouts in lower nodes, particularly TSMCN 7nm and below, is highly desirable. Proficiency in utilizing the latest features of Cadence VXL and Calibre DRC/LVS is expected. Basic knowledge of IO/ESD designs and familiarity with Basic SKILL/PERL will be beneficial for this role. The successful candidate should be capable of working both independently and collaboratively with a team, including contract workforces, to ensure timely completion of tasks. Effective communication skills are essential for working with global engineering teams. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application and hiring process. If you have the required qualifications and are interested in this position, please contact Qualcomm Careers for more information.,

Bachelors in Electronic/Electrical Engineering or equivalent Minimum of 5-10 years working experience in Semiconductor IC manufacturing Previous experience in T2000 system is a must Strong knowledge in Digital / Power-Analog / Mixed-signal Strong knowledge of C++ programming, and Windows Operating System Able to communicate effectively in spoken and written English Strong problem solving skills with some level of project management experience Possess a customer-focused attitude and have experience in customer management Engaged, self-directed and reliable to be willing to execute tasks on hand Self-driven attitude for continuous learning Willing to travel domestically and overseas Job Description: Provide pre/post-sales consultation for Advantest s T2000 Semiconductor Test System to customers. Resolve customer s pre/post production test program issues to minimize test system down time and time to high volume manufacturing. Understand customers IC testing needs and propose testing solutions to meet those needs. Develops and execute support plans as part of the customer account team. Lead test program development/productivity improvement projects based on customer s requirement. Deliver training programs to enable the customers to better utilize the T2000 system. Customer account management

Bachelors in Electronic/Electrical Engineering or equivalent Minimum of 5-7 years working experience in Semiconductor IC manufacturing Previous experience in 93000 system is a must Strong knowledge in Digital/Mixed-signal/RF IC testing Strong knowledge of C++ programming, Java, Linux and Windows Operating System Able to communicate effectively in spoken and written English Strong problem solving skills with some level of project management experience Possess a customer-focused attitude and have experience in customer management Engaged, self-directed and reliable to be willing to execute tasks on hand Self-driven attitude for continuous learning Willing to travel Provide pre/post-sales consultation for Advantest s 93000 Semiconductor Test System to customers. Resolve customer s pre/post production test program issues to minimize test system down time and time to high volume manufacturing. Understand customers IC testing needs and propose testing solutions to meet those needs. Develops and execute support plans as part of the customer account team. Lead test program development/productivity improvement projects based on customer s requirement. Deliver training programs to enable the customers to better utilize the 93000 system. Engage with customers to understand technical requirements, product roadmaps, and pain points. Deliver technical presentations, solution overviews, and value analyses to customers. Coordinate with R&D to tailor solutions that meet customer specifications. Drive early customer engagement and qualification efforts for new products and solutions. Coordinate cross-functionally with sales, engineering, and service teams.

Bachelors in Electronic/Electrical Engineering or equivalent Minimum of 5-10 years working experience in Semiconductor IC manufacturing Previous experience in 93000 system is a must Strong knowledge in Digital/Mixed-signal/RF IC Testing Strong knowledge of C++ programming, Java, Linux and Windows Operating System Able to communicate effectively in spoken and written English Strong problem solving skills with some level of project management experience Possess a customer-focused attitude and have experience in customer management Engaged, self-directed and reliable to be willing to execute tasks on hand Self-driven attitude for continuous learning Willing to travel domestically and overseas Job Description: Provide pre/post-sales consultation for Advantest s 93000 Semiconductor Test System to customers. Resolve customer s pre/post production test program issues to minimize test system down time and time to high volume manufacturing. Understand customers IC testing needs and propose testing solutions to meet those needs. Develops and execute support plans as part of the customer account team. Lead test program development/productivity improvement projects based on customer s requirement. Deliver training programs to enable the customers to better utilize the 93000 system. Customer account management

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node (

Bachelors / Masters degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in mixed signal IC verification / design experience Expertise in analog and mixed-signal circuit topologies Define verification plan based on product specifications and application use-cases Develop top-level AMS test benches using Cadence / System Verilog / UVM framework Simulate and validate verification plan use-cases Work with design team to debug and support issues Manage bug tracking Create automated regression flows Document and organize regression results Conduct AMS waveform review master the full AMS verification process. Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations

As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk Meeting EM/IR compliance requirements is essential You will ensure strict adherence to DRC, LVS, ANT, and density rules Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment. Basic Qualifications: Bachelor s degree or advanced diploma in Electrical Engineering (EE) Required Experience: 5+ years of experience in high-speed analog IC layout using Cadence Virtuoso Prior experience with BiCMOS layout is strongly preferred Proven experience handling at least one chip top-level through tapeout Proficiency in layout extraction and parasitic analysis for high-speed circuits Awareness of EMIR and antenna DRC rule-compliant layout practices Experience with Cadence SKILL and TCL scripting is highly recommended

The Allegro team is united by a clear purpose advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business from breakthrough product development and customer success to how we show up for each other and the communities we serve. The Opportunity As a Senior Layout Engineer at Allegro MicroSystems, you will be a key contributor to our integrated circuit development team, responsible for the physical implementation of complex analog and mixed-signal designs. You will work closely with design engineers to translate schematics into high-quality, manufacturable layouts, ensuring optimal performance and adherence to design rules. This role offers the opportunity to work on challenging projects, utilize advanced EDA tools, and contribute to the success of Allegros innovative products. You will operate with a high degree of autonomy, applying your expertise to solve intricate layout challenges and potentially mentor less experienced team members. What You Will Do Perform complex analog and mixed-signal IC layout from block-level to top-level integration, ensuring design rule compliance, matching, and performance optimization. Collaborate effectively with design engineers throughout the layout process, providing feedback and ensuring the physical design accurately reflects the circuit intent. Utilize advanced features of industry-standard Electronic Design Automation (EDA) tools, particularly the Cadence Virtuoso Design Environment (VDE) for layout, verification (DRC, LVS), and extraction. Apply a deep understanding of semiconductor process technologies (e.g., BCD, CMOS) and their impact on layout techniques for various analog circuits. Conduct thorough layout verification, including design rule checking (DRC), layout versus schematic (LVS), and parasitic extraction (PEX), and resolve identified issues. Contribute to floor planning activities and top-level assembly of integrated circuits. Identify and implement opportunities for layout efficiency and process improvements. Mentor and provide technical guidance to junior layout engineers, sharing best practices and contributing to team development. Document layout methodologies, design choices, and verification results comprehensively. What You Will Bring Bachelor of Science in Electrical Engineering (BSEE), Bachelor of Science in Engineering Technology (BSEET), or equivalent practical experience. Typically 5+ years of relevant experience in analog and mixed-signal integrated circuit layout. Demonstrated proficiency with Cadence Virtuoso Layout Suite, including schematic capture, layout editing, and verification tools (DRC, LVS, PEX). Solid understanding of analog layout fundamentals, including matching, shielding, low-noise techniques, and electro-migration considerations. Experience with layout of common analog building blocks such as op-amps, bandgap references, LDOs, ADCs, DACs, and power management circuits. Familiarity with semiconductor process technologies, ideally including BCD (Bipolar-CMOS-DMOS). Strong problem-solving skills and attention to detail. Ability to work independently and manage multiple layout tasks efficiently. Top level integration Analog On Top approach. Experience in R3D/ESRA or similar tools is a plus Experience with power analysis tools like voltusFi/mPower is a plus Python/skill code programming is a plus Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams.

Designing and developing physical layouts for high-speed analog and mixed-signal IP blocks including SerDes, RX, TX, PLL, and custom logic paths. Collaborating with a team of experienced layout engineers to deliver optimized, reliable, and manufacturable designs. Utilizing advanced CAD tools (Custom Designer, Cadence Virtuoso, Calibre, ICV, STAR-RXCT) for layout creation, verification, and debugging. Executing deep submicron layout techniques, including floor-planning, ESD/latchup mitigation, and process technology adaptation. Implementing and verifying layout flows such as LEF generation, top-level verification, DRC/LVS/LPE, and power routing with EM/IR considerations. Providing technical leadership through knowledge sharing, status updates, and networking with senior internal/external stakeholders. Applying scripting skills for layout automation to enhance productivity and reduce manual efforts. The Impact You Will Have: Delivering high-quality analog and mixed-signal IP layouts that enable next-generation silicon innovation. Elevating the performance and reliability of Synopsys IP portfolio through advanced layout techniques and verification processes. Driving successful tape-outs and product launches by ensuring robust design flows and manufacturability. Contributing to the technical advancement of the team with your expertise in deep submicron effects and process technology. Championing best practices in ESD/latchup mitigation, verification, and design for manufacturability (DFM). Fostering a collaborative culture by mentoring peers and sharing insights across cross-functional teams. Accelerating project timelines through layout automation and process optimization. What You ll Need: BTech/MTech in Electronics or Electrical Engineering. 6+ years of hands-on experience in analog/mixed-signal IP layout and verification for high-speed analog circuits. Advanced proficiency with CAD tools such as Custom Designer, Cadence Virtuoso, Calibre, ICV, and STAR-RXCT. Solid understanding of deep submicron effects, CMOS/FinFET process technologies, and advanced floor-planning techniques. Experience in layout design flow: LEF generation, DRC/LVS/LPE verification, power routing, EM/IR considerations, and DFM. Strong analytical, debugging, and troubleshooting skills; scripting experience for layout automation is a plus.

Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. Owning the full lifecycle of ESD structures from schematic design, simulation, and layout to silicon qualification and production release. Leading and executing I/O development, including I/O ring design, review, and optimization for performance and robustness. Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. Applying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality. Collaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions. The Impact You Will Have: Elevating the reliability and performance of Synopsys interface IPs, directly influencing the success of global semiconductor customers. Driving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry. Reducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions. Accelerating time-to-market for customer products through efficient and high-quality design practices. Fostering a culture of technical excellence and continuous improvement within the analog design team. Building strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects. What You ll Need: Proven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness. Hands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries. Strong background in ESD and Latch-Up qualification methodologies, including testchip development and validation. Proficiency in ESD simulation, ESD network construction, and use of industry-standard tools. Comprehensive understanding of PERC rules and practical experience with PERC verification tools. Experience working with cross-functional teams including foundry, design, and layout groups

1. Hands-on experiences on SV/UVM/Specman e 2. Familiarity w/ formal based verification 3. Running regression and debugging failures independently 4. Experience in functional and code coverages 5. Independently handling of sub-module level verification 6. These hires work with overseas teams need clear written/verbal communication skill 7. Familiarity on PIPE i/f or Ethernet is must, good to have basic knowledge on PCIe and/or high-speed Ethernet 8. Familiarity in mixed signal IP (SerDes, DDR) verification will be plus 9. Expected to work out of Cadence, Bangalore office

Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-stand ard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturabil ity and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.

Excellent opportunity for a hardware enthusiast who is looking for a unparallel growth that a start-up offers. Hardware Engineer - Motionmatics Hardware Engineer Excellent opportunity for a hardware enthusiast who is looking for a unparallel growth that a start-up offers. Noida Full Time Job Description Excellent opportunity for a hardware enthusiast who is looking for a unparallel growth that a start-up offers. 2 to 6 years of experience Strong hands-on: Board bring-up / Prototyping Circuit design HW troubleshooting Layout design (Multilayer, High speed, mixed signal) Understanding of microcontroller/FPGA/ICs Hands-on troubleshooting using DSO, multi-meters etc Dense circuits using FPGAs, Flash, RAM, SoC etc Responsibilities: Design & Development: Create and optimize electronic circuits and hardware components for new and existing products, ensuring performance and reliability. Prototyping & Testing: Build and test prototypes, analyse results, and implement design improvements. Documentation: Prepare detailed technical documentation, including schematics, layout designs, and test reports. Qualifications: Diploma or Bachelor s or Master s degree Proficient in CAD tools (e.g., Altium, Eagle), PCB design, and circuit simulation software. Familiarity with microcontrollers, embedded systems, and communication protocols (I2C, SPI, UART). MotionMatics is an equal opportunity employer. We value diversity and encourage applications from candidates of all backgrounds.

Job Description: Design and validate high-speed digital and mixed-signal circuits. Work on embedded system board design, including processor, memory, I/O. Handle design documentation, BOMs, and signal integrity validation. Interact with PCB layout engineers and fabricators. Support testing and bring-up activities for VPX/VME systems. Professional Skills / Technical Knowledge: Hands-on experience in Altium / OrCAD / PADS. Knowledge of SI/PI concepts, EMI/EMC considerations. Familiarity with MIL-STD design principles. Debugging and testing tools: Oscilloscope, Logic Analyzer, etc.

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

Roles & Responsibilities : Test program development on Advantest V93000 tester Test concept and specification development Release of Failure analysis test program Test time improvement. Test data analysis Yield improvement Supporting ramp-up development/measurements Qualifications BE / B.Tech/M Tech (ECE) 1) 8+ years of hands on experience with Advantest v93k Platform 2) Strong understanding on Analog / Mixed signal test methods. Debugging experience on ICs like Voltage Regulators, DAC, ADC, Power devices etc. 3) Familiarity with test hardware design 4) Familiarity with the tools like Altium, Orcad. 5) Should be a team player and flexible to travel to Germany for extended durations. Qualifications Educational qualification: BE/BTech ME/MTech Electronics and Communication Experience : 8 - 12 Mandatory/requires Skills : Preferred Skills :

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