142 Mixed Signal Jobs - Page 2

Electronic Hardware Designer As an electronic hardware designer, you will be designing and developing the hardware for the control and acquisition system of MR products, for hospital and outpatient radiology facilities. Together with other electronic hardware designers (RF, analog, digital and mixed signal), mechanical engineers, system engineering, manufacturing, and service engineers you will take products from concept through design into production to meet our customers needs. If you're passionate about healthcare innovation and cutting-edge technology, this is your chance to make a meaningful impact. Your role: You will be responsible for the design (models, schematics, and layout), realization, integration, and verification of analog and digital hardware components of the MRI systems. Deliver high quality hardware design starting from requirements till introduction in the factory, end to end. Actively participate in cost saving opportunities, design maintenance and solving end-of-life issues. Document development efforts for subsystem component and module, including requirements, specifications, design plans, reviews, test procedures and test reports. Coordinate, support, and execute product tests to provide a traceable verification of the product. Work Experience You're the right fit if: You hold a bachelors or masters degree in electrical or electronics engineering. 4-8 years of experience in electronic hardware development, preferably in a (safety) regulated industry (medical devices). You have experience with Electronic hardware design: analog- and mixed signal board design, power electronics design, communication interfaces, high speed digital interfaces, low noise RF signals, and PCB design tools (e.g. Cadence / Mentor Graphics). Electronic design simulation: SPICE based simulators, Advanced Design System, Microwave Office, Matlab, Ruby, Python. Electronic design practices: design for manufacturability and reliability, EMI/EMC standards, and design for six sigma. You have outstanding communication skills, are highly motivated and a good team player.

Title: Analog and Mixed Signal Design Engineer About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries make possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Analog and Mixed Signal Design Engineer to work in the Reference design team based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of analog circuit design blocks like BGR, LDO, OTA, Current mirrors Your Job: Sound foundation in Analog and Mixed signal circuit design in advanced silicon technologies Support silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Required Qualifications: MTech with more than 8 years experience or PhDs with 5 years experience from top tier institutes Applicants should have proficient knowledge of Analog circuit design and experience with EDA (Cadence, ADS) in silicon technologies SiGe and CMOS (bulk and SOI) Experience in analog blocks like OPAMP, OTA, Bandgap References (BGR), LDO, Biasing circuits with temperature compensation and mismatch aware circuit design Experience in layout and parasitic extraction Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects Preferred Qualifications: Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus Good publication and patent record Dedication and the ability to work within a very dynamic interdisciplinary environment Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional spoken and written Proficiency in English Strong analytical and problem-solving skills.

Title: Analog and Mixed Signal Design Engineer About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries make possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Analog and Mixed Signal Design Engineer to work in the Reference design team based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of analog circuit design blocks like BGR, LDO, OTA, Current mirrors Your Job: Sound foundation in Analog and Mixed signal circuit design in advanced silicon technologies Support silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Required Qualifications: MTech with more than 8 years experience or PhDs with 5 years experience from top tier institutes Applicants should have proficient knowledge of Analog circuit design and experience with EDA (Cadence, ADS) in silicon technologies SiGe and CMOS (bulk and SOI) Experience in analog blocks like OPAMP, OTA, Bandgap References (BGR), LDO, Biasing circuits with temperature compensation and mismatch aware circuit design Experience in layout and parasitic extraction Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects Preferred Qualifications: Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus Good publication and patent record Dedication and the ability to work within a very dynamic interdisciplinary environment Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional spoken and written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Seeking an experienced Analog IC design engineer for developing complex analog mixed signal/ high precision analog ICs for Power, Isolation and Infrastructure applications. This person will work in a design group at the forefront of Powering the A.I., EV and Energy revolution, working to develop technologies that will revolutionize various end markets by enabling new levels of power efficiency. Responsibilities Architects, designs, and verifies circuits, systems, algorithms, etc. to meet product requirements. Develops innovative new designs for patenting or protecting as trade secrets. Reports on design results through design reviews and weekly status meetings. Attends design reviews to provide input and learn from other designer s work. Research design techniques through technical publications and seminars. Develops scripts needed for automating design verification and thoroughly verifies their work before closing the task out. Responsible for custom layout including overseeing the work of layout designers. Works on bench characterization of silicon as needed to prove block/chip performance and to find issues with silicon. Communicates with cross functional team as needed to make sure all the assumptions made during design process are vetted properly. Helps recruit and grow the team, contribute to team building activities. Job Requirements Educational Background B.Tech + 5 years experience M.Tech + 3 years experience PhD + 0 years experience Minimum Requirements Knowledge of MOS transistors and analog circuit design Knowledge of complex AC/DC analysis (poles, zeros, compensation), loop dynamics and feedback systems Knowledge of device physics and CMOS/BiCMOS fabrication processes. Previous design experience with complex analog and mixed signal design blocks. Knowledge in signals, systems and transforms. Understanding of the end to end design flow from product definition to high volume manufacturing Understanding of layout tradeoffs for performance and size Knowledge of circuit simulation tools, layout verification tools, modeling tools, and UNIX Additional Skills (one or more of these are highly desirable) Previous design experience with high precision current/voltage references, bandgaps, regulators, ring oscillators, level shifters etc Knowledge of high voltage processes and design in BCD and/or SOI type processes MOS Device modeling skills (noise, excess thermal noise, DIBL) Laboratory measurement skills System knowledge (e.g., isolators) and design skills in system modeling Understanding of mixed signal solutions including discrete time digital signal processing Good written and verbal presentation skills Job Segment: Design Engineer, Electrical Engineering, Thermal Engineering, Manufacturing Engineer, Fabrication, Engineering, Manufacturing

Experienced PD Engineer working on mutliple technology nodes. Design for 40/22nm analog, RF, and mixed/signal circuits will be an added advantage. Perform layout from scratch, modify existing layouts. Create block level floorplans and work within the constraints of higher-level floorplans. Participate in peer and engineering reviews. Provide accurate area and schedule estimates for assigned circuit blocks. Work closely with both design engineers and other layout engineers. Required Experience and Skills We are looking for an experienced person (~10-15 years) who has overall knowledge of PD and takes care of all the flows associated with it. Apart from PnR & Synthesis: Experience with work closer to the front end such as digital modeling, gate level simulations, CDC, LEC, and STA/synthesis. Floor planning: Strategically planning the placement of functional blocks on the chip. Placement and Routing: Optimizing the placement of components and connecting them with wires (routing). Timing Closure: Ensuring the chip meets timing requirements (ensuring signals arrive at the correct time). Power Integrity: Managing power distribution and ensuring the chip operates reliably. Verification: Checking the layout for errors and ensuring it meets design rules. ECOs: Implementing design changes (ECOs) to fix issues identified during verification. Flow Development: Participating in developing and improving physical design methodologies and CAD tools. Job Segment: Front End, Design Engineer, Drafting, Network, CAD, Technology, Engineering

Role & responsibilities 1. HW Design Life cycle Experience 2. Digital and Analog design 3. Design Validation 4. Vendor Interaction 5. Good Communication Skill 6. Aero Experience is an optional requirement. 7. Cross function team interactions 8. Design Documentation preparation 9. Design Release process Aero Domain experience is preferred but not mandatory

CTO/Frontend Innovation/NVM Design Department is responsible for all embedded Non-Volatile Memory deployment across NXP business and product lines. Embedded NVM encompasses nearly all technology nodes and products which integrate Logic NVM, Flash or disruptive memory solutions (e.g. RRAM, MRAM). The implementation of Embedded NVM technologies that enhance application capabilities is a competitive advantage in the marketplace. In this position, we are looking for a design manager to build and lead an expansion of NXP s NVM design group in Bangalore, India. Are you able to create alignment, build, and lead a group of talented engineers to the next level? Can you ensure and facilitate that our employees get the best out of themselves to create innovative NVM IP that enables differentiating products? Scope of Responsibilities/Expectations As the Non-Volatile Memory Design Manager for our newly formed Bangalore team, you will be part of a Global NVM design department. You will be responsible for building a team of 10 to 20 engineers who will specialize in NVM Analog Design, Digital Design and Verification to support the deployment of Logic NVM, Flash and Disruptive Memory Solutions (RRAM, MRAM). The desired scope of work for the team covers definition, security, functional safety, NVM design, verification, deployment, validation support and industrialization. Job responsibilities: You will manage resource allocation and planning in close collaboration with our design management team and our project leads for innovation and IP developments. You will work with the Global NVM team and work partners to drive technical vision for cost-effective, fast time to market, and risk management for NVM IP. You will ensure compliance with your teams deliveries to our design flow and quality standards (BCAM, QMS, ISO 9001, ISO 26262, and CMMI). You will be an agent of change by identifying opportunities and deploying new methodologies in collaboration with the global team. You will nurture a high-performance culture within your team by employing NXP s performance management process. You will drive the development of your team accordingly to the competence and growth strategies. You will nurture and develop relationships with our business partners, foundry partners and 3rd party partners through internalized or collaborative innovation projects. Job qualification: BE or MS in Electrical/Electronics Engineering with 12+ years of design experience. Significant experience in leading an engineering team. Excellent communication skills with proven experience in international relationships and available for occasional travel. Hands-on experience in digital, analog, mixed-signal design and verification. Specific competence in NVM design and architectures is highly desired. Very good knowledge of quality managed design flows, tools and methodologies. Experience in developing and launching high volume mixed signal products into production including the automotive market.

Qualifications: Bachelor s or Master s degree in Electronics, Electrical Engineering, or a related discipline Proven experience in circuit design, analysis, and validation (analog, digital, mixed-signal) Proficiency with EDA tools (e.g., Altium Designer, KiCad, OrCAD, LTspice, Multisim, Fusion) Strong knowledge of measurement instruments and lab testing procedures (oscilloscopes, signal generators, etc.) Ability to diagnose and resolve complex hardware issues independently Excellent communication skills and ability to generate comprehensive technical reports

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . AMS Verification Lead - Isolation group Analog Devices is seeking an experienced Analog Mixed Signal Verification engineer to join its Interface Isolation group based at its Bangalore Research Development offices in India. The group is the market leader in galvanic safety isolation products due to its proprietary iCoupler transformers and More Than Moore wafer fabrication technologies. As these technology capabilities advance there is an emerging need for greater complexity in the digital and mixed signal verification requirements to bring next generation ground-breaking products to the Medical, Industrial and Test Measurement markets. Role Lead the AMS verification effort of devices Contribute towards verification strategy and methodology improvement Understand device requirements and come up with traceable AMS verification plan Hands on contribution to AMS top level verification effort Lead a team of AMS engineers/contractors Code/generate SVRNM models of required analog blocks and validate against schematic. Develop directed tests in AMS environment or reuse constrained random UVM testcases Interface with global design teams through various phases of verification File and track bugs to closure in Jira Document results of assigned blocks and review the results with the team Requirements Bachelor of Engineering degree in electrical/electronic engineering or comparable degree 8+ years experience in chip level AMS (analog mixed signal) verification of SOC Familiarity with latest digital verification methodologies like digital mixed signal verification(DMS) using UVM Experience with mixed signal simulators such as Cadence AMS or equivalent Experience in running GLS and scan sims from top level Experience with SVRNM or verilogams behavioural model coding for analog blocks Team player with good analyzing and debugging skills Open to adopting new tools and flows Must have good verbal and written communication skills to work effectively with teams spread geographically

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . AMS Verification Lead - Magnetic Sensors The mission of the Magnetic Sensor (MAG) team within the Industrial and Multi-Markets (IMM) Business Group is to develop highly innovative, differentiated and industry leading magnetic sensing technology for industrial and automotive markets. The novel and ground-breaking sensor products are defined and developed by the MAG team, leveraging proprietary processes in the Limerick Fab, meeting the emerging needs of our strategic customers. To help us accelerate our ambitious goals in bringing these emerging technologies to commercial success, the MAG team is seeking a highly driven and dynamic engineer to take a role as AMS Verification Lead responsible for leading package level design verification. The candidate will be responsible for formulating verification strategies, defining verification architecture, flow, methodology and leading, driving and completing verification of our sensor/ASIC solution. Requirements Bachelors/Masters degree in Electronics engineering or equivalent with 8+ years of experience Proven experience in leading full-chip level design verification of mixed signal devices Must have hands on experience in top level metric driven analog mixed signal (AMS) simulations Must have experience in modelling and validation of analog blocks (RNM, Verilogams etc.) Experience in developing verification collateral Familiarity with latest digital verification methodologies like digital mixed signal verification(DMS) using UVM Strong communication skills and ability to collaborate with a global team Role Setup mixed signal verification methodology/flow by interacting with methodology and CAD groups Understand device requirements and come up with traceable AMS and DMS verification plans Lead a team of AMS and DMS verification engineers/contractors Hands on contribution to modelling and AMS top level verification effort Technical support to team members Supervision of the DMS verification effort Interface with global design teams through various phases of verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary VPM is a sign-off tool for Low Power Design and Verification in custom mixed-signal IP designs. As a part of the VPM R&D team, you will be responsible for the design, development and maintenance of the cutting-edge products and features for low power design and verification in custom mixed-signal designs. You will be required to apply your software development, data structures and algorithms, skills along with the key concepts of the low power circuit design and verification to write and update, performance efficient code in C++ and Tcl programming languages, debug and fix code issues and develop and maintain unit and feature tests to test the software. The development environment is Linux so familiarity with Linux operating system, and commands, concepts of make file, UNIX shell scripting is also needed. The position also requires creating and reviewing functional specification for new VPM features using Microsoft Office Suite tools. You should be a team player willing to works with other members of the team as well and share your knowledge and learn from others. Knowledge of Low power designs and/or prior experience in EDA tool, QT, GUI and Tcl development would be a plus. Job Responsibilities Responsible for applying software development, data structures and algorithms, skills along with the key concepts of the low power circuit design and verification to design, develop, troubleshoot, and debug start-of-the-art software programs in C/C++/Tcl programming languages and shell scripting in Linux Operating system based development environment Create and review functional specification for new products and features using Microsoft Office Suite or equivalent tools Develop and maintain unit and feature tests to test the software. Improve stability, debug capabilities of the software Work independently and efficiently Works with other members of the team as well and share your knowledge and learn from others Continuously scale solutions (runtime, memory, number of CPUs etc. ) to take care of next-generation larger designs Engage with customers as needed and help in creative solutions Qualifications BE/BTech/ME/MS/MTech in Computer Science Engineering or Electrical Engineering or Electronics Engineering Experience and Technical Skills required Experience required : 2-4yrs Candidate must have experience of complex software development and maintenance using C/C++ Strong background in Software data structures and algorithms Must have excellent debugging skills and ability to separate out the critical issues from trivial ones. Familiarity with following is needed UNIX/Linux development environment, shell scripting, GNU gcc/g++ compilers, linters, linkers, make-file concepts debugging tools like GDB, DDD, or latest IDE, etc. Software memory and run time profiling tools, like valgrind, Kcachegrind, etc. , Static analysis tools like ASAN, Parasoft, ASAN, Microsoft Office Suite Experience in one or more of the following flows areas is a big plus: Custom Analog Design and Verification Low power design and Verification in custom mixed signal designs Knowledge of Low Power Specification formats like IEEE1801 (UPF), Liberty, Common Power Format, etc. Digital Implementation flow on advanced nodes EDA tool development Knowledge of QT, GUI and Tcl development Knowledge of scripting languages & Flow development Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: "¢ Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. "¢ 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). SRAM Mask Layout Designer Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm"™s high performance CPU team as an SRAM Mask Layout Designer? You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications — 5+ years of experience and a high school diploma or equivalent — OR 5+ years experience and BS in Electrical Engineering — OR 3+ years experience and MS in Electrical Engineering — Direct experience with custom SRAM layout — Experience in industry standard custom design tools and flows. — Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). — Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. — Knowledge of all aspects of Layout floorplanning and hierarchical assembly. — Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications — Good understanding of device parasitics and reliability considerations during layout. — Good understanding of critical circuits and layout styles. — Ability to write Skill code for layout automation. — Knowledge of improving EMIR in layout. — Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities — Design layout for custom memories and other digital circuits based on provided schematics. — Read and interpret design rule manuals to create optimal and correct layout. — Own the entire layout process from initial floorplanning to memory construction to physical verification. — Use industry standard verification tools to validate LVS, DRC, ERC etc. — Interpret the results from the verification suite and perform layout fixes as needed. — Provide layout fixes as directed by the circuit design engineers. — Work independently and execute memory layout with little supervision. — Provide realistic schedules for layout completion. — Provide insight into strategic decisions regarding memory layout and

Work Profile : - Work on development of custom Analog circuit boards for applications related to RF, interfaces etc. - Implement new features and bug fixes - Verify analog/mixed-signal integrated circuits - Develop test cases to verify new features and bug fixes - Review and update the user manuals for software tools. - Supporting digital modelling of analog circuits for mixed-signal verification - Creating design specifications and circuit schematics - Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team - Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements - Collaborate with others in the creation of technical reports, whitepapers, and user documentation Requisites : - EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges . - Strong knowledge of analog integrated circuit design fundamentals - Proven experience taking designs from concept to production - Experience in analog/mixed-signal IC design & verification - Understanding of BJT, CMOS and Op-Amp technologies. - Good understanding of analog/mixed-signal design flows (Cadence, Synopsys) - Transistor and system level simulation skills - Discrete time and continuous time signal processing skills - Strong lab and silicon validation skills - Verilog based digital design and test bench development, is a plus - Strong communication skills, both written and verbal

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced and passionate Analog Design Engineer with 1-3 years of experience in the field You have a strong background in CMOS processes and deep submicron process technologies You understand the intricacies of CMOS circuit design and layout methodology, and you have a basic understanding of analog/mixed signal circuitry Familiarity with ESD concepts is a plus You are knowledgeable about ASIC design flow and JEDEC requirements for DDR interfaces and standards You excel at executing circuit design tasks with a focus on quality and efficiency Your communication skills are excellent, enabling you to interact effectively with internal development teams, What Youll Be Doing: Designing DDR/HBM Memory Interface I/O circuits and layouts, including GPIO and special I/Os, Collaborating with the DDR/HBM PHY team, package engineers, and system engineers to meet design specifications, Ensuring adherence to best practices in circuit design and layout methodology, Conducting thorough design reviews and contributing to the continuous improvement of design processes, Staying updated with the latest advancements in analog design technologies and methodologies, Documenting design processes and providing support for design validation and testing, The Impact You Will Have: Enhancing the performance and reliability of our analog and mixed-signal circuits, Contributing to the development of high-performance DDR/HBM Memory Interfaces, Supporting the overall success of our chip design and IP integration projects, Driving innovation in analog design methodologies and processes, Ensuring our products meet the highest standards of quality and efficiency, Helping Synopsys maintain its leadership position in the semiconductor industry, What Youll Need: Bachelor's or Master's degree in Electronics or Electrical Engineering, 1-3 years of experience in CMOS processes and deep submicron technologies, Proficiency in CMOS circuit design and layout methodology, Basic understanding of analog/mixed signal circuitry, Familiarity with ASIC design flow and JEDEC requirements for DDR interfaces, Who You Are: A detail-oriented engineer with a passion for analog design, An effective communicator who collaborates well with cross-functional teams, A problem-solver who can analyze and address design challenges efficiently, A continuous learner who stays updated with industry trends and advancements, A team player who contributes to the overall success of the project, The Team Youll Be A Part Of: You'll join a dynamic and innovative team of engineers focused on advancing our analog design capabilities Our team is dedicated to pushing the boundaries of technology and delivering cutting-edge solutions for the semiconductor industry We value collaboration, creativity, and a commitment to excellence in everything we do, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Do you want to be part of our GaN success story? Do you want to work within a highly interesting field of engineering with interdisciplinary interfaces and be part of the biggest GaN development organization in the Semiconductor Industry? Do you strive for continuous improvement? If the answer to these questions is yes, then do not hesitate and join us at the pulse of technology as Senior Staff Engineer iGaN & IC Test Engineering. You will work in an international team being responsible for developing and implementing complex procedures for testing chip functionality and safety. This is the perfect position for someone who knows how to work fast and smart. Job Description Define test concepts and test specifications for Integrated GaN solutions in cooperation with the concept engineering and design team. Develop innovative test methods including DfT and optimize test software for the ATE (Automated Test Equipment). Design product specific test hardware for wafer and final test. Analyze, debug and characterize new products on the test system. Identify and introduce test package improvements to realize test time reduction and cost optimization. Transfer test packages to our production sites in Europe and Asia incl. intercontinental travelling (max. 10%). Provide production ramp-up support. Closely team-up with concept, design, verification, characterization, production and technology engineers. You are best equipped for this task if you have: A university / university of applied sciences degree in Electronics Engineering, Electrical or comparable work experience in IC and/or Wide Bandgap discrete test development engineering within the semiconductor industry Expertise in mixed-signal power test on Eagle ETS-88 or ETS-364 (or similar) and Advantest V93k is preferred Solid skills in analog or mixed signal electronic circuits and test program coding and debugging. Experience on testing of GaN or SiC power devices is a plus Fluent English skills (willingness to learn German is a plus) Technical driving skills, results oriented behavior and strong communication skills within global teams

Title : AMS Verification Engineer Location : Manipal/Bangalore Experience : 5 - 15 Years Salary : As per the Industry Key Responsibilities: Basic understanding of analog / mixed signal circuits ( like op-amps, amplifiers, current mirrors, LDO, ADC .. etc ). Understand the usage of cadence tools like Xcellium, Spectre, Simvision .. etc. Writing Verilog, Verilog-A/MS, Real Number Models. Develop/Use SV, UVM based Verification flows Understand metric based Verification closure using Code and Functional coverage Good scripting skills using perl, python is a plus. Must possess good communication, debugging skills and ability to work well in a team

Hiring electronics designer for Lighting company. Who is good in to electronics designing /PCB/ program manager etc. Pls share CV on sarika.vasdev@provisionconsulting.in

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74922 Description Responsibilities Work with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets. Participate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. Required Experience and Skills 5-10 yrs of relevant industry experience Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices A keen understanding of modern mixed-signal verification challenges and solutions. Solid foundation in network theory, amplifier design and data converters. Experience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs. Experience developing and maintaining chip level performance simulations of mixed-signal SOC designs. Ability to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions. Competent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs. Experienced in producing detailed technical reports and documentation. Experienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred. Experienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc. Simulation performance and accuracy trade-offs based on design requirements Experienced in Power-aware mixed-signal verification Hands-on verification of sub-45nm CMOS SOC designs Desired Experience and Skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Job Segment: Electrical Engineering, Design Engineer, Telecom, Telecommunications, Network, Engineering, Technology

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Applications Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Function Qualcomm is looking for candidates to support its customers in designing solutions using Qualcomm Hardware and Software. The Individual will contribute to the dynamic HW Applications engineering team for end product designs. The Individual will also be responsible for supporting Qualcomm's growing portfolio of platforms/applications and the job involves working closely with internal partners in Product definition as appropriate. About The Role The PMIC "“ H/W application Engineer will be responsible for supporting Qualcomm"™s growing portfolio mobile phone platforms. The job involves working closely with partners and customers of Qualcomm to define the specifications of the mobile phone handset products, part selection, system design, design reviews, support while doing system debug, partner deliverables etc. As a member of Qualcomm customer engineering team, the individual will be responsible for successful integration of Qualcomm solution into customer end products in mobile, PC, and consumer electronics markets. Individual will be responsible to work closely with cross function teams in Qualcomm, including design engineering, systems engineering, characterization team, ATE test team, SW team, product marketing, program management and peers in customer engineering organization across multiple regions. Individual will be responsible to create chipset documentation, reference schematics, training material, application notes for worldwide customer support. Individual will be responsible to engage with customer designs, assist customers in feature definition and design reviews, provide in-depth technical responses to customer queries, do troubleshooting of customer designs and provide necessary training to customers. Past expertise in interacting with multiple teams in HW, SW domains, skills in Digital/Baseband and sound technical knowledge of Qualcomm PMICs are desirable. . Preferred Qualifications Sound understanding of LDO/SMPS - Must to have Experience on power management for portable devices will be a plus Strong understanding PCB Signal/power integrity "“ Should be comfortable reviewing schematic/suggest changes for improvement - Experience with Schematic entry will be a plus . Should be fluent with CAD tools like Allegro/PADs to review customer layout . Knowledge on crystals/Clocks - Must to have Knowledge on display backlighting schemes - Must to have Knowledge on LabVIEW/python "“ Will be a plus Experience on Analog and mixed signal bench validation "“ Will be a plus Knowledge on battery charging and Fuel gauge will be a plus Good communication skills Keywords Power Management, Applications, Analog, PMIC, SMPS, DC/DC Converter, Buck, Boost, LDO, charger, fuel gauge/gas gauge, LED driver, ADC, oscillator, amplifier, Educational Requirements Bachelor's or Masters in Electronics and/or Electrical Engineering with 3 -5 years of relevant industrial experience

"> Search Jobs Find Jobs For Where Search Jobs ASIC Physical Design, Sr Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 4940 Remote Eligible No Date Posted 23/08/2024 Has a strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. He/She will be part of SNPS DDR/HBM/UCIe/Die-to-Die IP implementation team and responsible for the implementation and power signoff of world class DDRs at the cutting edge technology nodes. Timing closure above ~2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR power signoff would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Typically requires a minimum of 9+ years of related experience. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job. Frequently networks with senior internal and external personnel in own area of expertise. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design. You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structure, and interconnect failure modes in advanced finfet technology nodes. You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology. You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation. You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution. What you'll Be Doing: Leading Serdes analog design and development. Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What you'll Need: BE 18+ years of relevant experience or MTech 15+ years of relevant experience in mixed signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Strong fundamentals of CMOS, device physics, and sub-micron design methodologies. Experience with PLL designs and high-speed digital circuit design. Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experience in LC VCO/DCO design and performance parameters of VCO. Familiarity with digitally assisted analog circuit techniques. The Team you'll Be A Part Of: You will be joining an expanding analog/mixed-signal serdes team involved in the design and development of cutting-edge High Speed PHYSICAL Interface Development. You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

"> Search Jobs Find Jobs For Where Search Jobs Analog Design, Staff Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 5365 Remote Eligible No Date Posted 23/08/2024 Qualifications: Key Qualifications: Btech/Mtech with 4 -10 years of SerDes/High-Speed analog design experience. Experience in design of Analog front-end transceivers, voltage/current-mode drivers , delay-locked loop, phase-locked loop, Regulators, Equalizers (CTLE, FFE, DFE), Impedance calibrators, serializer , De-serializers , voltage-controlled oscillator, phase interpolator, bandgap reference, Clock data recovery circuits, Injection locked Loop etc. Hands ON experience with spice simulations and various sub-micron design methodologies. Familiarity with automation / Scripting language(TCL, PERL). Silicon-proven experience implementing circuits for analog and mixed-signal building blocks. Can micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit. Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). JOB Responsibilities Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Collaborate with digital RTL engineers on the verification of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

As our ideal candidate, you are a seasoned professional with a deep understanding of CMOS analog and mixed-signal Layout Design Engineering. You thrive in a collaborative environment and are passionate about pushing the boundaries of technology. With over 5 years of experience, you have honed your skills in designing complex PLLs, VCOs, charge pumps, and high-speed digital circuits Layout. You are detail-oriented, capable of coordinating with various teams, and have a proven track record of delivering high-quality designs. Your strong foundation in electrical engineering, combined with your innovative mindset, allows you to tackle diverse problems creatively and effectively. With excellent communication skills, you can articulate complex technical concepts to both technical and non-technical stakeholders, ensuring seamless collaboration and project success. What You ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits in PLL and other IP Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Define, design and develop complex RF clock path Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits. Drive innovation by developing cutting-edge layout designs that push the boundaries of technology. Enhance the manufacturability and reliability of our products through meticulous design and verification processes. Contribute to the overall success of our projects by providing valuable feedback during design reviews. Improve design methodologies and best practices, fostering a culture of continuous improvement. Support the growth and development of junior engineers by sharing your expertise and knowledge. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 7+ years of experience in A&MS layout design for integrated circuits. Hands physical design experience of passive elements used in PLL RC filter, LC oscillator Basic knowledge of PLL operating blocks Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented env Who You Are: Innovative thinker with a passion for technology and problem-solving. Excellent communicator, capable of articulating complex concepts clearly. Detail-oriented with a strong focus on quality and precision. Collaborative team player who thrives in a dynamic work environment. Adaptable and able to manage multiple priorities effectively

An Analog Design engineer works on conceptualizing, designing and productizing state of the art analog sensors. We are seeking an experienced, highly motivated, and high-caliber individual to work on design of on-chip Process, Voltage, Temperature, Current and Droop sensors as part of PVT sensor group. This individual should have strong technical experience in full custom analog/mixed-signal circuit design, circuit simulations, custom layout and post-silicon characterization. Additional responsibilities include: Development of new solutions in the field of on-die monitoring Liaising with layout team to achieve best possible engineering solution Deployment of new sensors into test chips and post-silicon characterization Guiding more junior engineers and tracking their work Job Requirements Design oriented and forward-looking thought process Sound knowledge of custom Analog/AMS design techniques, implementation and verification B.Tech. or M.Tech. degree in Electrical Engineering with 5+ years of relevant industry experience or Phd with relevant experience. Awareness of full custom layout techniques Exposure to advanced process challenges, including ESD and Reliability Exposure to architecture, design and verification of PVT, Oscillators, Bandgap, PLLs, LDOs, ADCs, Amplifiers, PHYs and other Mixed-signal blocks Excellent teamwork, communication, mentoring, and interpersonal skills with both internal teams and external customers Preferred skills : Strong custom design experience - specification, circuit design description and schematics Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies