156 Mixed Signal Jobs - Page 7

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

Leading the development of next-generation DDR/HBM/UCIe IPs. Advising team members to meet schedules and resolve problems effectively. Taking on project leadership roles and contributing to complex project aspects. Developing and maintaining project schedules, ensuring timely delivery. Collaborating in cross-functional settings to drive project success. Demonstrating proficiency in design and verification processes. The Impact You Will Have: Driving innovation in next-generation DDR/HBM/UCIe IP development. Enhancing the performance and capabilities of our Silicon IP portfolio. Ensuring high-quality and efficient project execution. Mentoring and guiding team members to achieve their full potential. Contributing to the rapid integration of advanced technologies into SoCs. Helping Synopsys maintain its leadership in the semiconductor industry. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or a related field. 8+ years of experience in CMOS circuit design and layout methodology. In-depth understanding of analog/mixed-signal circuitry and ESD concepts. Familiarity with analog mixed-signal simulation strategies. Knowledge of JEDEC standards for DDR interfaces and ASIC design flow. Who You Are: Visionary leader with strong problem-solving skills. Excellent communicator with the ability to lead and mentor teams. Detail-oriented and proficient in project management. Adaptable and able to thrive in cross-functional settings. Committed to achieving high standards of product quality and efficiency

An experienced and passionate Layout Design Sr Engineer with a strong background in Analog and Mixed Signal Circuit Layout. You possess a deep understanding of semiconductor device physics and have hands-on experience in EDA tools for custom mixed signal layout flows. Your expertise in CMOS and FINFET technologies, coupled with your knowledge of CMOS fabrication technology, equips you to handle deep sub-micron effects and their impact on layout. You are self-directed, detail-oriented, and have excellent problem-solving and communication skills. Your enthusiasm for learning and exploring new layout techniques drives you to innovate and excel in your role. What You ll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You ll Need: Bachelors or masters degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus. Who You Are: Self-directed and detail-oriented. Excellent problem-solving skills. Strong communication skills. Passionate about learning and exploring new layout techniques

The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. K EY RESPONSIBLITIES : Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. P REFERRED EXPERIENCE : Years of experience 13+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills. Strong digital design knowledge. Exposure to UPF based low power RTL verification. Prior experience in leading a team is desirable. Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits. You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation. Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work. You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools. Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset. What You ll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.