242 Mixed Signal Jobs - Page 6

About the Role This leadership position is pivotal within a global digital data business, contributing to the development of next-generation connectors, cable assemblies, and radio system components. Youll steer a specialized engineering team focused on Signal Integrity, guiding end-to-end product lifecycle activitiesfrom concept to high-volume manufacturing qualificationthrough rigorous design, simulation, and testing. This is more than managementit's strategic direction in a fast-evolving tech space where innovation and precision meet performance. Click to Apply - (https://forms.gle/fqb29wUvjNuV82C57) Responsibilities Strategic Leadership: Lead a globally distributed team of experienced SI engineers. Align design activities with organizational goals, customer expectations, and technical standards. Create and manage work plans, project schedules, budgets, and resource allocation. Technical Oversight: Define signal integrity performance parameters for innovative products. Guide complex simulations for multiple protocols: PCIe, USB, Ethernet, etc. Oversee connector design reviews using electromagnetic simulation tools and test validation data. Ensure adherence to qualification processes for high-speed connector interfaces and cable assemblies. Innovation & Execution: Integrate market trends and customer needs into technical roadmaps. Advocate a data-driven design culture through structured simulation reviews and continuous improvement. Lead advanced packaging and PCB layout exploration to support emerging high-speed protocols. Team Development: Build a cohesive, skilled team through talent assessments, structured onboarding, and continuous upskilling. Foster collaboration across geographies and functional disciplines (mechanical, process, materials, product). Provide clear coaching, feedback, and career development plans. Balance workloads and promote wellbeing through flexible, effective leadership. Key Technologies & Tools Signal Integrity Tools: Agilent ADS, Ansys HFSS, CST CAD Platforms: SpaceClaim, AutoCAD, Creo PCB Design: Altium, layout/fabrication validation Test Equipment: VNA, TDR, BERT Data Analysis: Statistical interpretation, tolerance modeling Simulation Interpretation: Channel modeling, S-parameter validation Ideal Candidate Profile 10+ years in electrical or RF design with progressive experience 3+ years of people management and cross-functional leadership Strong grasp of physical layer system architecture and packaging interfaces Skilled communicator able to present to technical and executive audiences Experienced in high-volume manufacturing qualification and risk analysis Proven success building high-performance teams with global collaboration

Physical Design- Hyd Leads(8+years) AMS, 180nm or 90nm above DC-DC, buck boost convertor/PMIC Job Title: Lead Physical Design Engineer Job Description Skills requried: Good Experience in 14nm and above with DC- DC converter or buck boost converters, LDOs, Op-Amps and Blocks • In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. - Should have experience in Analog and Mixed Signal Design Should have experience in handling >5M instance count , 1.5GHz frequency designs. • Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. • Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) • Strong experience on Static Timing Analysis (PrimeTime - SI) , EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). • Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements. • Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74911 Responsibilities Work with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets. Participate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. Required Experience and Skills 5-10 yrs of relevant industry experience Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices A keen understanding of modern mixed-signal verification challenges and solutions. Solid foundation in network theory, amplifier design and data converters. Experience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs. Experience developing and maintaining chip level performance simulations of mixed-signal SOC designs. Ability to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions. Competent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs. Experienced in producing detailed technical reports and documentation. Experienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred. Experienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc. Simulation performance and accuracy trade-offs based on design requirements Experienced in Power-aware mixed-signal verification Hands-on verification of sub-45nm CMOS SOC designs Desired Experience and Skills Job Segment: Electrical Engineering, Electrical, Design Engineer, Network, Telecom, Engineering, Technology

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities: Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication. Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Position Requirements B.S. in Electrical Engineering (M.S./Ph.D. preferred) 4-7 years of experience in practical analog/mixed signal design for image sensors or other relevant areas. Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Knowledgeable in ADC architectures for image sensor readoutRelevant experience with bandgaps, bias, op-amps, switched-cap circuits, LDOs, PLL, SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experienced in all stages of mixed-signal chip design (preferably in the context of image sensors) flow including DFT, timing analysis, top chip integration and tapeout, and silicon bring up. Experience leading a design team is highly preferred. Excellent communication skills are required.

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Looking for PCB layout design Engineers with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Hands-on experience with High-speed interfaces like DDR3,DDR4, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constrains setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Educational Qualification: B Tech/M. tech/BE/ME, Diploma Location: Hyderabad Shift: General Exp.: 4-6 Years Work Week: Monday to Friday

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Looking for PCB layout design Engineer with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Exposure with complex 2U, 3U server form factor-based PCB designs. Hands-on experience with High-speed interfaces like DDR3,DDR4/5, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constraints setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file collaboration with Mechanical Engineer. Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Education Requirements: B. Tech/B.E./M. Tech./M.E. Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

Contribute to the development of new HBM products by assisting with verification of analog and mixed signal blocks. Full chip verification activities: ERC, analog test mode bits trim, power amps functionality, pin difference and high voltage or current in circuits related checks Defining methodology and full chip verification flows for 2.5D stacked dies Power up checks: powerup sequence, voltage level, leakage current and forward bias condition check Reliability related items: Advanced FinFET (3nm, 5nm, 12nm) devices related stress and reliability check Analog IP specific items: Understand analog block functionality, propose stimulus, increase coverage, develop flows to improve verification (capture missed corners, failing boundaries etc) Behavior modeling: Analog behavior model development to assist full chip verification Design guideline related checks Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality. Mentor and lead young designers.

Reporting to: Lead Engineer. Job Description. Create Schematics using Computer-Aided Design Altium/ Eagle platform tools.. Create PCB Circuit layouts and documentation from schematics using Altium/ Eagle tools considering Layer Stack up, Multilayer Board, EMI/EMC checks, High Speed Design etc.. Designed up to 8 layers. Worked in Mixed signal, powerboard, RF boards of placement and routing with guidelines.. Important High-Speed Interfaces: Processor, DDR3, USB3, MIPI CSI-DSI, EMMC, SDIO and wireless interface antenna Layout Design. Worked on protecting high frequency signals and clock signals from interfacing and noise by providing ground guarding. Knowledge on Layer Stack-up for Impedance control boards, Power boards and High Speed SOC Board. Knowledge on using blind and buried vias.. Process PCB , Flex and rigid-flex Circuit layouts for pattern generation, documentation, and Computer-Aided Manufacturing (CAM) files for fabrication and assembly. Work closely with Product Design Engineers, Mechanical Engineers, and Designers to produce the optimal PCB and for power supplies distribution layout, and other product circuits. Produce and maintain all documentation and engineering drawings for PCB Circuit designs. Creating PCB footprints SMD & Through hole as per IPC standards and component library Development.. Design Rule check and net list analysis to generate error free net list. Incorporate Engineering Change Orders (ECOs) to PCB Circuit designs.. Uses tools to calculate dimensions and tolerances to assure function, fit, and manufacturability of components and assemblies, and performs component research to recommend design alternatives, and contributes to technical designs and documentation.. Maintain the record of PCB design and its revision.. May perform other duties as assigned. Provide support to collaborate with Electronics Manufacturing Service vendors. Familiar with communication protocols such as USB, I2C, SPI, UART, I2S and implementation practices of the same on PCB Layout. Diverse experience in multicore microcontroller/ microprocessor based circuit design and bring-up. Ideally from ST/TI/NXP/Embedded OS based SOC and sensor interface on PCBA level.. Qualification. Degree/Diploma holders in Electronics and Telecommunication. 5+ years of experience in PCB designing using Altium tool.. Hands on experience in Alitum Library Management. Good understanding of Electronics part and their packages. Good communication skill. Show more Show less

Exciting opportunity for freshers to work on RFIC Circuit, Layout & PCB Design using industry-grade EDA tools. Get industry exposure, grow technically, and build your semiconductor career.

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will involve all phases of a design project, including specification and architectural design, detailed digital block design, simulation, verification, and design bring-up and test. This role involves collaborating with cross-functional teams to ensure that the design meets specifications. The candidate will also be expected to interface with customers to communicate specifications, design status, technical details, etc. Primary Responsibilities: Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Design architecture and RTL coding of digital blocks, with complex operating modes. Participate in design verification, chip bring-up, and debugging in the lab by writing scripts, analyze data, and propose experiments, etc. Create and maintain detailed documentation of design processes, methodologies, and best practices. Participate in technical reviews with design team and customer. Able to work independently and collaborate with local technical lead. Work with test engineers to facilitate development of test hardware, test plans, and participate in block level bring-up and characterization efforts and results. Position Requirements Bachelor s or master s degree in electrical engineering, computer engineering, or a related field. 3-5 years of experience in RTL design, mixed signal concepts, and verification, with a strong understanding of the entire ASIC design flow. Strong knowledge of digital design principles, front-end tools, clock design, datapath, timing analysis of CMOS digital circuits, Verilog, SystemVerilog. Strong knowledge of FPGA design, firmware development for test systems, and high-speed data transmission. Working knowledge of synthesis, static timing, DFT is a plus. Proficiency in scripting languages such as Perl, Python, or Tcl for automation. Excellent problem-solving abilities, with a keen eye for detail and a methodical approach to debugging and optimization. Effective communication skills, with the ability to collaborate with cross-functional teams and present technical information clearly. Ability to adapt to new tools, technologies, and methodologies, staying current with industry trends and advancements.

Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Forza s history begins at the formation of the CMOS imaging industry where company co-founders, Barmak Mansoorian and Daniel Van Blerkom were a critical part of the Photobit team. Along with Photobit Co-founder, Dr. Eric Fossum, and many others, the team pioneered the development of CMOS imaging technology. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza Silicon has grown to where today the company employs one of the industry s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com Postition Summary: This position will report to the engineering manager and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This position will involve all phases of a design project, including specification and architectural design, detailed circuit design, simulation, layout, verification, and design bring-up and test. The candidate will also be expected to interface extensively with customers and external vendors to communicate specifications, design status, technical details, etc. Primary Responsibilities: Oversee all phases of sensor design: specification, design and tapeout, test, transition to product. Work with customers to understand sensor requirements, translate requirements to detailed specifications, and develop sensor architecture to ensure specifications are met. Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner. Perform detailed circuit analysis, design, simulation, layout, verification of mixed-mode circuits Interface with foundry partners to understand process details in support of design implementation, manage pixel design and performance, and oversee tapeout and fabrication. Work with test engineers to facilitate development of test hardware, test plans, and oversee chip bring-up and characterization efforts and results. Position Requirements B.S. in Electrical Engineering (M.S./Ph.D. preferred) 6-8 years of experience in practical analog/mixed signal design for image sensors or other relevant areas. Expert at transistor level circuit design, simulation, verification using modern EDA tools from Cadence, Siemens, Synopsys, etc. Knowledgeable in ADC architectures for image sensor readout Relevant experience with bandgaps, bias, op-amps, switched-cap circuits, LDOs, PLL, SERDES, high-speed TX, general feedback, and compensation techniques. Expert in noise analysis, transistor/capacitor matching and sources of errors in analog integrated circuits. Experienced in all stages of mixed-signal chip design (preferably in the context of image sensors) flow including DFT, timing analysis, top chip integration and tapeout, and silicon bring up. Experience leading a design team is highly preferred. Excellent communication skills are required.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. E view modeling Characterization Verilog behavior modeling, timing lib modeling, Power view modeling, model verification of mixed signal analog IPs like DDR-MSIP, DDRIOs,. SERDES analog, ADC/DAC, PLLs e.t.c. . Functional understanding of mixed signal analog IPs as above for modeling and Characterization verification Proficiency in Verilog modeling and verification. Write behavioral Verilog/Verilog MS/real models of analog blocks. Developing and maintaining the self-checking Test-benches /Test-Plans. SV modeling and testbench development for verification against transistor level netlist Proficiency in Simulators such as VCS e.t.c. 5+ years of experience with characterization tool and simulators like Silicon Smart, Hspice, Finesim, Nanosim and Liberty format description Basic skills on AMS verification and knowledge preferable Self-motivation, teamwork, and strong communication skills. Tcl/Perl/Skill Scripting aware for automation You may e-mail or call Qualcomm's toll-free number found . To all Staffing and Recruiting Agencies :

Role & responsibilities Job Description Must have: Lead the verification of analog and mixed-signal IPs such as bandgaps, LDOs, multi-phase buck regulators, comparators, and functional safety (FuSa) monitoring circuits. Own and execute comprehensive verification plans for assigned blocks or features, ensuring complete coverage and robust test quality. Develop or enhance analog behavioral models using System Verilog Real Number Modelling (SV-RNM). Validate digital functionalities including CRC checks, clock monitors, register maps, OTPs, and communication interfaces. Apply strong SystemVerilog skills, including the use of assertions and cover groups. Utilize advanced debugging techniques across RTL and schematic views at the top level. Manage and maintain VSIF files to support verification regression workflows. Conduct coverage analysis using tools such as IMC or vManager. Write or maintain automation scripts (Make files preferred) to streamline verification processes. Work independently with minimal supervision, managing tasks and priorities effectively. AMD (Dont Share AMD Profiles) Preferred candidate profile

We're looking for a highly experienced and self-motivated Lead Analog/Mixed-Signal Verification Engineer to join our team. In this pivotal role, you'll be responsible for the comprehensive verification of complex mixed-signal designs, from block to full-chip levels. You'll drive verification methodologies, mentor junior engineers, and play a crucial part in ensuring the quality of our cutting-edge products. Responsibilities: Lead the verification of complex mixed-signal designs and sub-systems , ensuring robust functionality and performance. Develop and utilize Analog Behavioral Models (SystemVerilog, Verilog-AMS, wreal, UDNs, EEnet) for efficient verification. Validate real number models against SPICE models , ensuring accuracy and correlation. Gain hands-on experience with SPICE simulations using industry-standard simulators such as SPECTRE. Define comprehensive test plans, tests, and verification methodologies for both block and chip-level verification of Mixed-Signal Designs. Continuously interact with the analog co-simulation team to enable seamless top-level chip verification. Contribute to and influence decisions on verification methodologies to be adopted across projects. Technically mentor and guide junior verification engineers on SoC Verification best practices. Support post-silicon verification activities of products, working closely with design, product evaluation, and applications engineering teams. Required Qualifications: B.Tech/M.Tech with 8-12 years of industry experience in analog/mixed-signal verification. Demonstrated experience in verification plan development, verification environment creation, and verification/debug of complex mixed-signal products at block and chip-top levels. Proven experience in co-simulations with analog model/transistor level and digital RTL/Gate+SDFs , as well as circuit simulations with Spice/Fast Spice simulators. Proven experience in leading full-chip level design verification of mixed-signal devices. Must have experience in modeling and validation of analog blocks (RNM, Verilog-AMS, etc.). Familiarity with latest digital verification methodologies , including Digital Mixed-Signal (DMS) verification using UVM. Strong communication skills and the ability to collaborate effectively with a global team. Self-motivated and enthusiastic. Excellent debugging and analytical skills. Additional Qualifications & Experience: Proficiency with Verification Planning tools (e.g., ePlanner, vManager). Experience with SystemVerilog Assertions (SVA) . Skilled in scripting languages (Shell, TCL, Perl, Python) for testbench automation. Hands-on UVM experience at the user level, including pseudo and constrained random techniques, and assertion-based verification with SystemVerilog. Experience in building and leading small verification teams . Strong interpersonal, teamwork, and communication skills are essential.

Lead development efforts for AMS design collaterals generation fortop level integration, ensuring optimized performance Job Description In your new role you will: Lead development efforts for AMS design collaterals generation for top level integration, ensuring optimized performance. Enforce consistency of all required views for AMS macro integration. Ensure quality of digital design deliverables to RTL2GDS counter parts by running preliminary RTL synthesis and timing checks. Identify and apply methodologies to allow optimal timing closure of complex AMS IP (ADCs, clocking) in the context of digital-on-top integration. Collaborate with cross-functional teams, including digital design,AMS design, layout, and test engineers, to ensure successful productintegration. Interface with design system community, design flow and methodologyteams across multiple sites (Europe, US and Asia). Validate AMS views generation flow to guarantee smooth execution incase of design system and/or design package updates. Your Profile You are best equipped for this task if you have: Master s or Ph.D. in Electrical Engineering or a related field. 15+ years of experience in complex AMS & SoC integration within thesemiconductor industry Proven track record of successful product implementation in advancedCMOS and BCD technologies Deep technical knowledge of mixed-signal IC design and integrationflows Very good understanding of RTL2GDS flows and experience in runningsynthesis, timing closure, DFT insertion Ability to work in a multinational environment and connect designteams with RTL2GDS and SoC integration teams across the organization Ability to support project planning and commitment to ensure timelyexecution. Ability to report progress and issues related to SoC integration tosenior executives

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm’s high performance CPU team as an SRAM Mask Layout DesignerYou will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications 5+ years of experience and a high school diploma or equivalent OR 5+ years experience and BS in Electrical Engineering OR 3+ years experience and MS in Electrical Engineering Direct experience with custom SRAM layout Experience in industry standard custom design tools and flows. Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. Knowledge of all aspects of Layout floorplanning and hierarchical assembly. Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications Good understanding of device parasitics and reliability considerations during layout. Good understanding of critical circuits and layout styles. Ability to write Skill code for layout automation. Knowledge of improving EMIR in layout. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities Design layout for custom memories and other digital circuits based on provided schematics. Read and interpret design rule manuals to create optimal and correct layout. Own the entire layout process from initial floorplanning to memory construction to physical verification. Use industry standard verification tools to validate LVS, DRC, ERC etc. Interpret the results from the verification suite and perform layout fixes as needed. Provide layout fixes as directed by the circuit design engineers. Work independently and execute memory layout with little supervision. Provide realistic schedules for layout completion. Provide insight into strategic decisions regarding memory layout and

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: AMS Verification Location : Bangalore Work Type: Onsite Job Type: Full time Job Description: Lead the verification of analog and mixed-signal IPs such as bandgaps, LDOs, multi-phase buck regulators, comparators, and functional safety (FuSa) monitoring circuits. Own and execute comprehensive verification plans for assigned blocks or features, ensuring complete coverage and robust test quality. Develop or enhance analog behavioral models using System Verilog Real Number Modelling (SV-RNM). Validate digital functionalities including CRC checks, clock monitors, register maps, OTPs, and communication interfaces. Apply strong SystemVerilog skills, including the use of assertions and cover groups. Utilize advanced debugging techniques across RTL and schematic views at the top level. Manage and maintain VSIF files to support verification regression workflows. Conduct coverage analysis using tools such as IMC or vManager. Write or maintain automation scripts (Make files preferred) to streamline verification processe TekWissen Group is an equal opportunity employer supporting workforce diversity.

Bring substantial experience in effective team management to help mentor, coach and grow the Physical Design and Implementation team with an emphasis on positive influence on team morale and culture Will be responsible for delivering silicon for a wide range of applications Primarily a management position, however, the candidate is required to have significant RTL to GDSII knowledge to probe into technical details Candidate will be required to collaborate and foster good relationship with all parts of engineering: Architecture team, Front End Design teams and Program management Qualifications Minimum 15 years of ASIC physical design experience Minimum 5 years of management experience with leading a physical design and implementation teams from RTL-to-GDSII Should have excellent collaboration and teamwork capabilities across various chip development disciplines. Will be responsible to hire talent and mentor, build expertise, and grow each team member Ability to define and drive flows and methodologies to optimize physical design work, define guidelines and checklists, drive execution, and track progress Ability to resolve design and flow issues related to physical design through the identification of potential solutions and drive resolution Experience in working with the front-end teams to understand chip architecture and drive physical aspects early in the definition cycle Experience working relationships with EDA Vendors Multiple successful tape out Excellent communication (oral and written) skills Ability to present to and interface with internal customers Ability to handle a dynamic environment and to coordinate team action Bachelor s Degree in Electrical Engineering or closely related discipline is required Masters Degree in Electrical Engineering or closely related discipline is preferred Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world s most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Waltham, Massachusetts; Vancouver, Canada; Valencia, Spain; Bangalore and Chennai, India; Villach, Austria; Munich, Germany; Israel; and Singapore. We have approximately 1,500 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.

We are seeking a Principal Analog Design Engineer to lead the architecture, design, and development of Power Management ICs (PMICs). This is a high-impact technical leadership role, focused on designing complex, high-performance analog and mixed-signal circuits with emphasis on quality, reliability, and innovation. Key Responsibilities Define architecture and lead transistor-level design of analog and mixed-signal blocks for PMICs, including: LDOs, DC-DC converters (Buck/Boost), Voltage supervisors, Power sequencing, Load switches, Bandgap references, Oscillators, and Bias circuits Drive system-level specification and partitioning in collaboration with Systems and Application teams Perform pre- and post-layout simulations and analysis across PVT corners using industry-standard EDA tools Work closely with layout engineers to optimize performance, area, and noise/EMI sensitivity Collaborate with cross-functional teams across design, verification, test, validation, and reliability Ensure designs meet functional safety, reliability, and regulatory compliance standards Support silicon bring-up, characterization, and debug Mentor junior designers and lead design reviews Promote IP reuse, documentation best practices, and patent/IP generation initiatives Qualifications Bachelor s, Master s, or PhD in Electrical Engineering or related field 15+ years of hands-on experience in analog/mixed-signal IC design, with a focus on PMICs Deep expertise in analog circuit design, power management, and system-level integration Familiarity with ISO 26262, AEC-Q100, and other quality/reliability standards Strong experience with Cadence tools and analog simulation methodologies Demonstrated leadership in delivering complex designs from concept to production Excellent problem-solving, communication, and collaboration skills Experience with high-voltage BCD processes (e.g., 40V/60V) Proven track record of successful silicon tape-outs and production ramp Knowledge of industry design standards and practices for reliability and safety Understanding of layout impact on analog performance and EMC/EMI mitigation We recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer: Disability/Veteran Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 6 to 9 years experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc, Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc) Understanding layout effects on the circuit such as speed, capacitance, power and area etc Ability to understand design constraints and implement high-quality layouts Ability to understand design hierarchy and different architectures for Memory designs. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills.

Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tape out. Experience: 7-15Y Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floor planning is a plus Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.