142 Mixed Signal Jobs - Page 6

In your new role you will: Be in continuous and intensive contact with our development sites worldwide Advise and support the experts from our business units in verification projects Drive the internal exchange of know-how and experience at Infineon Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment for ICs using the "Universal Verification Methodology" (UVM) Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the low-power aspects of our designs You are best equipped for this task if you have: You have a degree in Electrical Engineering, Computer Science or a similar academic discipline. You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification. You have experience with microcontroller-based ICs and ideally with security and safety requirements. You are experienced in the creation and dissemination of methods in the area of functional verification. You have an excellent understanding of and application skills in UVM and UPF. You have sound knowledge of firmware and RTL design (VHDL) - experience with Cadence verification software is a plus. You have some initial experience in technical leadership and project management. Contact: Swati.Gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans, Mentoring Junior engineer - Partial Ability to drive MSV project independently Drive enhancements in known methodologies You are best equipped for this task if you have: Bachelors with 5+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Working with a design team to develop advanced DRAM and Emerging memory products using state-of-the-art memory technologies. - Verifying high-density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high-speed designs, and complex functionality. - Evaluating block level functionality/fullchip level and providing solutions for functionally correct design. - Collaborating with various design and verification teams across the globe. - Providing verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing and maintaining test benches and test vectors using simulation tools and running regressions for coverage analysis and improvements. - Participating in the development of new verification flows for challenges in DRAM and emerging memory design. - Developing verification methodology and verification environments for advanced DRAM and emerging memory products. - Understanding and using digital/mixed signal circuits and verification tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice. - Writing Verilog and Real Number Models. - Building SV testbenches at Block and Fullchip Level. - Using SV, UVM based Verification and scripting using Perl and Python. - Previous work experience in DRAM memory related fields is preferred. - Good communication, debugging skills and ability to work well in a team are required. - Understanding the usage of tools like Cadence (Xcellium, Simvision), Synopsys (VCS, Verdi), and Mentor (Questasim) simulators.

Job Title: Hardware Design Engineer Location: Onsite - Gurugram (Manesar), Delhi/NCR Company: AutoBitNex (Automotive Electronics & Embedded Systems) Experience Level: 4+ Years Job Overview: AutoBitNex, a growing automotive electronics startup , is seeking an experienced Hardware Design Engineer with 4+ years of industry experience to join our onsite hardware development team. This role focuses on embedded systems design, schematic design, component selection (BOM), PCB layout, and hardware verification for automotive and non-automotive embedded systems . The ideal candidate must have expertise in power electronics, digital electronics, microcontrollers (MCUs), and communication interfaces , ensuring compliance with industry standards and best practices . Key Responsibilities: 1. Embedded Systems Design, Schematic Design & BOM Selection Develop schematic diagrams for embedded systems using Altium Designer . Select and integrate microcontrollers (MCUs), processors, sensors, and power electronics components . Optimize the Bill of Materials (BOM) for performance, cost, and manufacturability. Ensure component compatibility and sourcing feasibility . 2. PCB Layout & Design Design multi-layer PCBs with considerations for signal integrity, EMI/EMC, and thermal management . Ensure Design for Manufacturing (DFM) and Design for Assembly (DFA) best practices. Work with high-speed, low-power, and mixed-signal circuit designs . 3. Power Management & Signal Integrity Design and optimize power electronics circuits such as DC-DC converters, LDOs, and SMPS . Analyze and mitigate power integrity, ground loops, and EMI/EMC issues . Ensure compliance with ISO 26262 (Functional Safety), IEC, and automotive industry standards . 4. Prototyping, Testing & Hardware Verification Develop and test hardware prototypes for functional and performance verification . Conduct board bring-up, debugging, and failure analysis . Perform thermal, mechanical, and electrical verification . Ensure compliance with EMI/EMC, ESD, and regulatory standards . 5. Collaboration & Cross-Functional Coordination Work closely with firmware, mechanical, and system engineering teams for seamless embedded system integration. Collaborate with vendors and manufacturers for component sourcing and PCB fabrication. Document designs, specifications, and test reports for traceability and future reference. Required Skills & Qualifications: Component Knowledge: Strong understanding of passive and active components , including inductors, capacitors, resistors, transformers, relays, MOSFETs, diodes, RF components, BJTs, IGBTs, FETs, ferrite beads, crystal oscillators, varistors, thermistors, optocouplers, zener diodes, TVS diodes, and supercapacitors . Ability to select components based on power, signal integrity, frequency response, thermal requirements, and environmental conditions . Education: Bachelor's/Masters in Electronics, Electrical, or Embedded Systems Engineering . Experience: Minimum 4+ years in hardware and embedded systems design. Technical Skills: Proficiency in Altium Designer (mandatory). Strong knowledge of microcontrollers (MCUs), power electronics, and digital electronics . Experience with communication interfaces (CAN, UART, SPI, I2C, Ethernet) . Expertise in EMI/EMC compliance and high-speed PCB design . Hands-on experience with hardware debugging tools (oscilloscopes, logic analyzers, spectrum analyzers) . Preferred: Experience with automotive industry standards (ISO 26262, IEC, AEC-Q100) . How to Apply: Application Requirements: Candidates must mention the following details in their email: Current CTC Expected CTC Notice Period Email your resume to careers@autobitnex.com Subject Line: "Application for Hardware Design Engineer Role" Join us in shaping the future of automotive and embedded systems hardware solutions at AutoBitNex! #Jobs #JobOpenings #Hiring #EngineeringJobs #HardwareDesignJobs #HardwareDesign #EmbeddedDesign #Altium #Schematic #HardwareDesignEngineer #PowerElectronics #DigitalElectronics #Onsite #Startup

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts review critical items. Contribute to effective project-management. Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background BE or MTech in Electronic/VLSI Engineering 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm 5+ exp ****

In your new role you will: As an Analog Mixed-Signal Verification / Validation Engineer for power products Work with design, application, and systems teams to generate test requirements and define test methodologies. Plan and participate in future technologies and projects. Designing of the boards required for testing Power ICs consideringpower and signal integrity aspects. Measurement of datasheet parameters for Power IC s(Controllers,drivers, current sensors) Debug issues related to IC functioning and parametric failures, androot causing the issues with help of design team. Usage of different type of instruments used in LAB (DMM,Oscilloscopes, Power Supplies, AFG etc) Drive innovation in the form of new advancements (test methods/tools,test automation, test infrastructure) Development of Python Scripts for Test Automation. Collating measurements data and analysing it to find anomalies,trends and identify potential issues in design. Work with Test/Product teams in debugging and correlating the resultsbetween the ATE and Bench platforms. You are best equipped for this task if you have: A Master s /bachelor s degree in Electrical/Electronic Engineering or equivalent field of studies. Relevant 5 years of experience in Analog and Power products Verfication / Validation Good Analytical skills and understanding of Analog Circuits Experience in board layout designing in Altium/Cadence allegro. Experience in development of scripts in Python for Test automation will be plus. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision with fluency in English #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity Inclusion at Infineon.

About The Role : Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications Qualifications: B.Tech 7+ years & M.Tech 5+ years or PhD having hands-on experience in high-speed analog circuit design, with a proven track record of successful projects. Expertise in designing and verifying analog circuits such as High-speed transmitter, receiver, amplifiers, PLLs, voltage regulators, and data converters. Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to various Business Units/SoCs within AMD. The ideal candidate will get to work with Circuit and FE Architects on the design and implementation of complex high speed Analog Mixed Signal IPs with significant Digital and Analog content. K EY RESPONSIBLITIES : Architect the analog-digital interface timing boundary for high-speed analog mixed signal IP designs. Design high speed custom digital sub-modules for high-speed DDR PHY classes and die-to-die PHY. Use the performance-power-reliability trade off matrix to achieve IP goals. Define the appropriate margining methodology and scope for data, clock and async timing paths. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design and/or flow fixes. Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays in deep-nm tech nodes for various types of data interfaces and clock propagation schemes. Provide technical guidance to junior team members. Use scripting skills to meet efficiency and quality goals across all timing workflows. P REFERRED EXPERIENCE : 12+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Experience with SerDes or DDR PHY digital logic layer implementation is required. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop analysis. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Strong communication skills with ability to ability to comprehend and present ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess fundamentals and knowledge of analog mixed signal circuits, timing collaterals and constraints. Proficient in AMS design flows, tools and methodologies. Experience in evaluating and adopting new tools and methodologies to improve design processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (eg UCIE) to various Business Units/SoCs within AMD. The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals. KEY RESPONSIBILITIES: Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Use the appropriate margining methodology for data, clock and async timing paths to improve timing robustness and reliability. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design fixes. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Use scripting skills to meet efficiency and quality goals across all timing workflows. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays for various types of data interfaces and clock propagation. Prepare, analyze and report on data integrity and consistency within the macro timing model using spice correlation and data analytics. PREFERRED EXPERIENCE: 6+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop. Strong communication skills with ability to comprehend and present technical ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess sound fundamentals and knowledge of analog mixed signal circuits timing collaterals and constraints. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Your primary focus will be to lead Test Engineering Characterization teams across sites with focus on development, implementation and execution of Characterization test programs for various Automotive Microcontroller Products. In your new role you will: Lead Test Engineering Teams across sites Work closely with cross-functional teams to ensure stakeholder alignment in Post-Silicon methodology related to chip characterization. Drive cost reduction and quality improvements by optimizing characterization concepts, test programs and test hardware. Make Post-Silicon Characterization cost competitive with respect to project timeline and scope. Provide requirements on ATE capabilities derived from new productroad maps. Ensure timely execution of the Characterization Test Program meeting Project milestones. Build and manage high-performance teams driving innovation and process improvements. Foster a culture of innovation and continuous improvement through out the organization. You are best equipped for this task if you have: 8+ years of hands-on experience in any of the post silicon domains (validation, characterization, test engineering) is preferred. Experience in analog mixed signal domains is preferred. 3years of experience in leading and managing teams of a reasonable size. Preferred experinece in managing cross-site projects

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

The Customer Support Business Group focuses on enabling our customers with premier customer support throughout their lifecycle with Lam. We drive performance, productivity, safety, and quality of customers installed base performance and deliver service and lifecycle solutions for their most critical equipment and processes. The Impact You ll Make The role of Electrical Engineer 3(Technical Lead) within the Customer Support Business Group (CSBG) of LIGHT organization. This high energy individual will focus on development and support for Productivity and Technology Upgrades to our global customers through Engineering projects (EPLs) for Deposition and Etch product lines. Meet Corporate metrics and goals set to achieve excellence and deliver fast solutions to our global Customer What You ll Do Responsible for executing CSBG Electrical Engineering activities (DPL s/EPL s /PPL s) & provide technical support to team as on when required. Proficient with use of in Zuken E3S CAD software to Design cable harness schematics, electrical Schematic and system interconnects diagrams. Creates electrical schematics and system based on requirements and creates/releases engineering drawings & bill of materials Responsible for performing professional electrical engineering research, design, development, modification, and testing in support of electrical systems and / or power distribution, down to the discrete circuit and PCBA level. Selection of Electrical & Electronics OEM components and materials for Power distribution, I/O Controllers, Sensors, Cables, PCBs etc. Accept technical responsibility for the electrical design projects and D&D team working on the DPLs Who We re Looking For Educational Qualification & Relevant Exp. Guidance: Bachelors degree (or equivalent) in electrical & electronics engineering or electronics & communication engineering with minimum of 10+years of related experience; or master s degree with minimum 8+ years of experience Well versed with Part life cycle management, Obsolescence management activities. Proficient in system level understanding of Electro-Mechanical Sub-systems, Power Distribution/Control systems and/or Industrial Automation. Proficient in Electrical & Electronic Circuit design with safety interlocks & various circuit analyses. Hands-on experience in Low/High Voltage Electrical & Electronic circuit designs for Power and Control applications Must have worked on any one of electrical engineering CAD tools like ZUKEN. Preferred Qualifications Experience in selection of components, setting up equipment for experimentation / testing in laboratory environment, setting up safe practices Experienced in system level understanding of Electrical architecture, IO Controllers and Applications Good communication skills and experience of working in cross-functional teams in a matrix organization Hands on experience with various equipment s like mustimeter s, function generators, mixed signal oscilloscopes, analyzer Familiar with PCB Applications for control panel Design & Knowledge in Engineering Change Management Process

About The Role : Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Has more than a year of relevant work experience. Solid understanding of programming concepts, software design and software development principles. Consistently works to direction with minimal supervision, producing accurate and reliable results. Individuals are expected to be able to work on a range of tasks and problems, demonstrating their ability to apply their skills and knowledge. Organises own time to deliver against tasks set by others with a mid term horizon. Works co-operatively with others to achieve team goals and has a direct and positive impact on project performance and make decisions based on their understanding of the situation, not just the rules. Skills (competencies) Verbal Communication

Exciting Career Opportunity for Senior Manager, Digital/RTL Design (ASIC) Location: Bangalore, India Experience: 12+ Years Work Mode: Hybrid (3 days from the office) Company: A Leading Japanese Semiconductor Manufacturing Company Are you a seasoned Digital ASIC Design professional ready to take on a leadership role? We are seeking a Senior Manager Digital ASIC Design to join one of the worlds top Japanese Semiconductor Manufacturing companies in Bangalore. This is a unique opportunity to work on cutting-edge ASIC designs in a dynamic and innovative environment. Please Note: This role is exclusively for ASIC design (not FPGA or IT-related digital design). Key Responsibilities: Digital Design Leadership: Oversee and manage the Digital Design team, including resource planning, methodology development, and staffing, to support device/silicon design requirements and deliver on program deadlines . Mixed-Signal IC Expertise: 12+ years of experience in Digital Design , with a strong focus on Mixed-Signal ICs , particularly Power Management ICs (PMICs) . Define Digital-Analog boundaries and outline the Digital design scope for Analog-intensive ICs . Design & Architecture: Define micro-architectures and sub-blocks to enable optimized Digital design , RTL design , and Gate-level netlist development. Manage Clock Domain Crossing (CDC) across multiple clock domains while ensuring glitch-free operation. Technical Collaboration: Lead and collaborate on Logic Synthesis , Formal Verification , Power Estimation , and Static Timing Analysis (STA) . Drive the development of OTP, MTP, Efuse read/write , controller design, data bus management, and DFT architecture/integration . If you are passionate about leading advanced Digital Design and driving innovation , we want to hear from you! Apply Now! Send your resume by clicking "Apply" and sharing your CV. Lets connect on LinkedIn: linkedin.com/in/heena-kausar-3a2b94a4 Tag your connections who might be interested! Join us and shape the future of semiconductor technology !

About Marvell . Your Team, Your Impact The Central Engineering Foundational IP team is responsible for Layout design of SerDes IPs and Foundational IPs. What You Can Expect As a key member of Marvells Central Engineering team, you will play a leading role on developing next-generation high speed SerDes IPs. We work with leading edge finfet technologies to produce best-in- class analog IPs which enable us to move, store, process and secure the worlds data faster and more reliably than anyone else. What Were Looking For Bachelors or Masters Degree and or PhD in Electrical/Electronics Engineering, Microelectronics or related fields. 4 to 8 years of related professional experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experiences in one or more of the following area is preferable : Mixed signal/analog/high speed layout, e. g. SerDes, ADC/DAC, PLL, etc. Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 32nm/28nm/16nm/14nm and FinFET is preferable. Experience with EMIR analysis, ESD, antenna and related layout solutions. Good communication skills and willingness to work with global team. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment. Programming skills, automation and circuit Design background is a plus. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional P ost Silicon Validation Engineer to join our memory interface chip design team in Bangalore In this role, you will be responsible for the validation and bring-up of high-speed memory buffer semiconductor products. You will collaborate closely with silicon design teams, develop test methodologies, and lead the analysis of lab data to ensure product performance meets specifications. The ideal candidate will have experience in post silicon validation, lab automation, and strong problem-solving skills. Responsibilities Silicon bring-up and validation process of high-speed memory buffer semiconductor products. Develop, implement, and refine test methodologies for validating silicon designs. Create and maintain automation scripts to control lab equipment and facilitate efficient data collection. Independently troubleshoot issues found during validation and provide solutions. Lead experiments and drive the collection of relevant data to meet validation milestones on schedule. Work closely with silicon design and validation teams to understand design specifications and performance targets. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 3-6 years of experience in analog and mixed signal validation, high speed IO characterization. Hands-on experience with I2C and I3C protocols. Experience in working with DDR, LPDDR, or high-speed memory validation is a plus. Proficiency in using lab equipment such as oscilloscopes, BERT, and signal generators. Strong scripting skills (Python, Perl, or similar) for automation of tests and data analysis. Experience in design and debug hardware boards for post-silicon validation. Excellent problem-solving skills and the ability to troubleshoot complex hardware and software issues. Strong communication skills and ability to work effectively in cross-functional teams. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.