242 Mixed Signal Jobs - Page 10

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Looking for PCB layout design Engineer with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Exposure with complex 2U, 3U server form factor-based PCB designs. Hands-on experience with High-speed interfaces like DDR3,DDR4/5, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constraints setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file collaboration with Mechanical Engineer. Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Education Requirements: B. Tech/B.E./M. Tech./M.E. Experience: 5 to 8 Years Location: Hyderabad Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

Roles & Responsibilities: Supporting in development of new product, re-design and value engineering of existing products. Execute VAVE study and identify the cost out opportunities which are quality neutral. Design schematic of digital, mix signal & power electronics circuits to meet the requirement. PCBA prototyping, board bring-up and test, debug. Create the design documents, validation and test plan mapping to the requirements. Provide detailed requirement for FCT of PCBA to make sure meet design requirement. Essential Skills: Analog: Precision amplifiers, Thermocouples and RTD, Pressure and flow sensors, High speed ADC and DAC. Power: LDOs, Switching regulators, High voltage circuits and AC-DC converters. Communication/Data interface: SPI, I2C, LVDS, USB, Ethernet Processor: ARM processor family, FPGA and CPLD Component Engineering: Component life cycle and RoHS, Reach compliance. Full time experience in digital and analog hardware design with advanced microcontroller, FPGA/CPLD, high speed ADC and DAC. Good experience with PCBA process and board bringup. Strong knowledge in alternate design analysis/part substitute for cost out ideas including design analysis for functional, quality and reliability. Experience in practices for Design for Test (DFT) and Design for Manufacturing (DFM). Proficient in test and debugging instruments like DSO, logic analyzer, spectrum analyzer and EMI/EMC test simulators. Hands on experience on EDA Tools like Altium, OrCAD and Mentor Graphics etc. Qualification/s: BE/BTech or MTech / ME in Electrical / Electronics Engineering or similar

Nature of Assignment / Roles & Responsibilities: Supporting in development of new product, re-design and value engineering of existing products. Execute VAVE study and identify the cost out opportunities which are quality neutral. Design schematic of digital, mix signal & power electronics circuits to meet the requirement. PCBA prototyping, board bring-up and test, debug. Create the design documents, validation and test plan mapping to the requirements. Provide detailed requirement for FCT of PCBA to make sure meet design requirement. Requirements Essential Skills: Analog: Precision amplifiers, Thermocouples and RTD, Pressure and flow sensors, High speed ADC and DAC. Power: LDOs, Switching regulators, High voltage circuits and AC-DC converters. Communication/Data interface: SPI, I2C, LVDS, USB, Ethernet Processor: ARM processor family, FPGA and CPLD Component Engineering: Component life cycle and RoHS, Reach compliance. Full time experience in digital and analog hardware design with advanced microcontroller, FPGA/CPLD, high speed ADC and DAC. Good experience with PCBA process and board bringup. Strong knowledge in alternate design analysis/part substitute for cost out ideas including design analysis for functional, quality and reliability. Experience in practices for Design for Test (DFT) and Design for Manufacturing (DFM). Proficient in test and debugging instruments like DSO, logic analyzer, spectrum analyzer and EMI/EMC test simulators. Hands on experience on EDA Tools like Altium, OrCAD and Mentor Graphics etc.

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Hands on with any of the spice simulators (Hspice/ Spectre)

Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Master s degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical backgroun

We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor s or Master s degree in Electronics or Electrical Engineering

Embedded product hardware design expertise (Electrical and electronic product domain). Knowledge on latest Product Design technologies & trends- H/W. Design experience of Mixed-signal hardware design. Should have expertise in various Power Supply Design topologies. Expertise in using various hardware design simulation tools. Should have sound knowledge for complying the products for EMI/EMC standards (CE, RE, CS, RS and others) Excellent Analytical & problem solving skills Electronic component knowledge and selection of proper components as per design requirement.

Roles and Responsibility 4 to 8 years of experience in pre-silicon verification or respectively a mixture of senior and junior engineers Experience using SystemVerilog/UVM for Digital Functional or Mixed Signal Verification. Proficience in using SystemVerilog for design and verification. Solid experience using state of the art tools and methodologies (Xcelium, vManager, Certitude etc) Create and maintain verification plans. Experience setting up verification environments and implementing functional coverage model. Ability to elaborate, execute and debug tests on RTL level, as well as on Gate Level. Experience with automotive quality expectations Experience with Jira/Jama Extra skill as a plus: Experience with CPU verification or protocol verification (SPI, I2C, CSI2, LVDS etc) Knowledge in Digital Signal Processing and Digital Filters.

Design analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs Job Description In your new role you will: Design analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs including POR, Bandgap, LDO, Oscillators, drivers,current sensing, test modes etc. Assist in defining the requirements for analog and mixed-signal blocks , aligning them with IP Module architecture, and ensuringcompliance with requirements through documentation. Provide essential support to physical design engineers, post-silicon validation, production testing, and other critical activities extending beyond the design phase. Communicates with cross functional/inter disciplinary team as needed to make sure the team is aware of the assumptions and progress made by the design team. Balance innovation with execution: to ensure that the projects aredelivered in a timely manner. Your Profile You are best equipped for this task if you have: A Master s degree in Electrical/Electronic Engineering, microelectronic, or comparable with focus on electronics. 5+ years of experience in analog IC design with proven track record of delivering high performance DC-DC converter Power IC solutions. Good Analytical skills and very good understanding of Analog Designlike biasing, small signal and large signal analysis. Proficiency with industry-standard design verification and simulation tools. Understanding of process technologies and device behavior which are important for high voltage, high power operation and reliability issues.

The Allegro team is united by a clear purpose advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business from breakthrough product development and customer success to how we show up for each other and the communities we serve. The Opportunity As a Senior Principal Analog Design Engineer at Allegro MicroSystems, you will be a pivotal technical leader within our design organization. You will leverage your deep expertise in analog integrated circuit design to drive the development of highly complex and innovative solutions for our next-generation products. This role requires not only exceptional technical acumen but also the ability to mentor junior engineers, define architectural strategies, and significantly influence product roadmaps. You will tackle the most challenging design problems, contributing directly to Allegro's market leadership and technological advancements. What You Will Do Lead the architecture, design, simulation, and verification of complex analog and mixed-signal circuits for high-performance integrated circuits, from concept to mass production. Drive the definition of circuit specifications, block-level partitioning, and top-level integration strategies. Perform advanced circuit analysis, modeling, and simulation using industry-leading EDA tools (e.g., Cadence Virtuoso, Spectre, AMS, Verilog-A/AMS). Provide technical leadership and mentorship to less experienced engineers, fostering their growth and ensuring design quality across the team. Collaborate closely with system architects, digital design engineers, layout engineers, test engineers, and product marketing to ensure successful product realization. Develop and implement innovative design techniques and methodologies to achieve aggressive performance, power, and area targets. Lead design reviews, critically evaluating designs, providing constructive feedback, and ensuring robust design practices are followed. Oversee silicon characterization, debug, and validation activities, driving root cause analysis for complex issues. Contribute to intellectual property generation through invention disclosures and patent applications. Stay abreast of the latest industry trends, technologies, and competitive landscape, applying this knowledge to influence future product definitions and technology roadmaps. What You Will Bring Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field. Typically 10+ years of progressive experience in analog integrated circuit design, with a proven track record of successfully bringing complex ICs to market. Deep expertise in the design of a wide range of analog building blocks, such as high-performance op-amps, ADCs/DACs, PLLs, bandgap references, LDOs, power management circuits, and sensor interfaces. Extensive experience with advanced semiconductor process technologies, including BCD (Bipolar-CMOS-DMOS) and deep sub-micron CMOS processes. Proficiency with a full suite of EDA tools for schematic capture, simulation, layout, and verification (e.g., Cadence Virtuoso, Spectre, AMS, Calibre, Quantus). Strong analytical and problem-solving skills, with the ability to tackle complex technical challenges independently and collaboratively. Demonstrated leadership capabilities, including mentoring, technical guidance, and influencing cross-functional teams. Excellent communication skills, both written and verbal, with the ability to present complex technical information clearly and concisely. Ability to work effectively in a fast-paced, dynamic environment and manage multiple priorities.

MTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (e.g. UCIE) to various Business Units/SoCs within AMD. The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals. KEY RESPONSIBILITIES: Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Use the appropriate margining methodology for data, clock and async timing paths to improve timing robustness and reliability. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design fixes. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Use scripting skills to meet efficiency and quality goals across all timing workflows. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays for various types of data interfaces and clock propagation. Prepare, analyze and report on data integrity and consistency within the macro timing model using spice correlation and data analytics. PREFERRED EXPERIENCE: 6+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop. Strong communication skills with ability to comprehend and present technical ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess sound fundamentals and knowledge of analog mixed signal circuits timing collaterals and constraints. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2

NVIDIA Silicon Solutions Group is looking for an experienced Engineer to coordinate multi-functional post-silicon development and validation of high speed SERDES for our brand new GPUs. You will join a motivated and skilled global HW team and play a key role in delivering high-quality, brand new GPU products to cater to different markets. You will get to work on characterization efforts of IOs such as PCI-E,USB, UFS, Ethernet, NVLINK; Own power characterization and Optimization of interfaces, System level functional testing for performance and system stability What you ll be doing Develop and Own the planning and execution of functional and electrical bring up, system level feature validation, corner qualification and resulting debug of SERDES on NVIDIA GPUs Address scheduling conflicts, update program guides, handle blocking issues from customers, improve manufacturing yield, and gather design feedback Coordinate with logic design, circuit design, board design, Simulation, diagnostics, ATE, firmware, driver and marketing teams to align product specifications. Develop new methodologies to improve the quality and efficiency of silicon validation process of analog/mixed signal IPs. What we need to see: BTech/BE and a minimum of 3 years of proven experience Strong experience in High Speed interconnect solutions on servers and datacenter systems and topologies, including quality and reliability Excellent knowledge of Signal Integrity concepts, Jitter, Silicon manufacturing characteristics and high-speed electrical characterization interfaces (any of PCIe-gen5, USB3, Thunderbolt, SAS, DDRx, or similar protocols Detailed knowledge of lab/measurement equipment (DSOs, BERT, VNA, Protocol analyzers) is required Background with automation scripting in languages such as Perl, Python, tcl Must be a standout colleague and ready to engage with global teams from diverse cultural backgrounds in a high energy environment #LI-Hybrid

Join SanDisk India as a Technical ASIC Project Leader and take charge of developing the cutting-edge ASICs that power the next generation of the USB storage solutions. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Master s degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical background in digital design, verification, and silicon validation with good understanding of the USB, PCIe, ONFI standards and peripherals. Excellent cross-functional leadership and communication skills. Ability to manage technical risks and drive execution in a fast-paced environment. Passion for innovation and delivering high-quality, scalable solutions. Preferred Qualifications: Proficiency with EDA tools and methodologies for ASIC development. Familiarity with industry standards and best practices in semiconductor design. Expertise in low-power design techniques and high-speed interfaces.

Where Analog Design, Sr Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12426 Remote Eligible No Date Posted 06/08/2025 We Are: You Are: You are a passionate and detail-oriented engineer with a strong foundation in CMOS analog and mixed-signal circuit design. You thrive in collaborative, high-impact environments and are motivated by the challenge of developing cutting-edge silicon solutions. With a solid background in deep submicron process technologies, you understand the nuances of DDR interfaces and the importance of robust, scalable, and high-performance circuit design. You are adept at balancing innovation with reliability, ensuring that your designs meet stringent quality and efficiency standards. Your experience enables you to approach complex problems methodically, and you are always eager to stay ahead of technology trends, continuously learning and applying new knowledge to your work. You value open communication and are comfortable working across diverse, global teams. You believe that inclusion, diversity, and mutual respect are essential to driving the best outcomes. Whether you re mentoring junior engineers, collaborating with peers, or interacting with cross-functional partners, you demonstrate professionalism, empathy, and a drive for excellence. Above all, you are excited to contribute to solutions that power the smart, connected world of tomorrow. What You ll Be Doing: Designing and developing advanced DDR I/O circuits for next-generation SoCs, focusing on performance, power efficiency, and reliability. Executing end-to-end circuit design tasks, including schematic capture, simulation, layout, and design validation. Collaborating with cross-functional teams to integrate analog and mixed-signal IP blocks into larger system architectures. Ensuring compliance with JEDEC standards for DDR interfaces, including timing, ODT, and SDRAM functionality. Conducting design reviews, analyzing process variations, and implementing robust design-for-manufacturability strategies. Documenting design methodologies, contributing to continuous improvement, and sharing best practices within the team. Providing technical guidance and mentorship to junior engineers and interns. The Impact You Will Have: Enable the rapid integration of high-quality analog IP into complex SoC designs, reducing time-to-market for customers. Drive design innovation that meets the evolving demands of performance, power, and area in advanced semiconductor technologies. Ensure the delivery of robust and reliable DDR I/O solutions that meet or exceed industry standards. Support Synopsys position as a global leader in silicon IP by delivering differentiated, high-performance products. Contribute to customer success by addressing application-specific requirements and providing technical expertise. Promote a culture of knowledge sharing, technical excellence, and continuous improvement within the engineering team. What You ll Need: BTech (with 2+ years of experience) or MTech (with 1+ years of experience) in Electrical/Electronics Engineering or related field. Strong understanding of CMOS process technologies and deep submicron design challenges. Proficiency in analog and mixed-signal circuit design, including layout methodologies and flow. Experience with DDR interface design, JEDEC standards, DDR timing, ODT, and SDRAM functionality (a plus). Familiarity with ASIC design flow and ESD concepts. Demonstrated ability to execute complex design tasks efficiently and with high quality. Who You Are: Analytical thinker with strong problem-solving skills and attention to detail. Effective communicator, both written and verbal, comfortable interacting with global teams. Self-motivated, proactive, and adaptable to rapidly changing project requirements. Team player who values diversity, inclusion, and knowledge sharing. Continuous learner, eager to adopt new tools, methodologies, and industry best practices. The Team You ll Be A Part Of: You ll join a dynamic, collaborative team of analog and mixed-signal designers focused on delivering state-of-the-art DDR I/O and silicon IP solutions. Our team thrives on innovation, technical excellence, and a supportive culture that encourages growth, creativity, and cross-functional collaboration. Together, we tackle complex challenges and enable Synopsys to lead in the rapidly evolving world of semiconductor technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer ! Onboarding Welcome! !