142 Mixed Signal Jobs - Page 3

You are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors You thrive in a collaborative environment and have a knack for solving complex problems Your strong technical expertise in full custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization sets you apart You are a forward-thinking individual who is always looking for innovative solutions and has excellent communication and mentoring skill You possess a BTechor MTech degree in Electrical Engineering with over 5 years of relevant industry experience, or a PhD with relevant experience You have a deep understanding of custom Analog/AMS design techniques, implementation, and verification, and you are familiar with the challenges of advanced processes, including ESD and reliability What You ll Be Doing: Developing new solutions in the field of on-die monitoring. Liaising with the layout team to achieve the best possible engineering solutions. Deploying new sensors into test chips and conducting post-silicon characterization. Guiding and mentoring junior engineers and tracking their work. Conceptualizing, designing, and productizing state-of-the-art analog sensors. Collaborating with cross-functional teams to ensure successful project execution. The Impact You Will Have: Contributing to the development of next-generation intelligent in-chip sensors. Enhancing the performance, power, area, schedule, and yield of our customers products. Improving the reliability of various target applications through innovative solutions. Advancing the field of on-die monitoring with cutting-edge technologies. Driving the integration of full hardware IP, test, and end-to-end solutions. Supporting the continuous technological innovation that powers the Era of Smart Everything. What You ll Need: Strong technical experience in full custom analog/mixed-signal circuit design. Proficiency in circuit simulations and custom layout techniques. Experience with post-silicon characterization and deployment of new sensors. Sound knowledge of custom Analog/AMS design techniques, implementation, and verification. Awareness of advanced process challenges, including ESD and reliability. Who You Are: A forward-thinking engineer with a design-oriented mindset. An excellent team player with strong communication and interpersonal skills. A mentor who can guide and support junior engineers. A problem solver who thrives in a collaborative environment. A lifelong learner who stays updated with the latest industry trends and technologies.

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 10+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required

Leading the development of next-generation DDR/HBM/UCIe IP. Providing guidance and mentorship to team members, ensuring project schedules are met and problems are resolved efficiently. Acting as a project leader, contributing to complex aspects of IP development. Developing and maintaining project schedules, collaborating with cross-functional teams. Designing and verifying CMOS circuits and layouts. Implementing analog mixed-signal simulation strategies and ensuring signal integrity. The Impact You Will Have: Driving the development of cutting-edge IP that powers the future of technology. Enhancing the capabilities of SoCs, enabling faster integration and reduced risk for customers. Contributing to the success of Synopsys by delivering high-quality IP on time. Leading a team of talented engineers, fostering innovation and excellence. Ensuring the highest standards of product quality and efficiency. Playing a key role in the Era of Smart Everything, from AI to IoT. What You ll Need: BTech/MTech degree in a relevant field. 8+ years of experience in analog design. Knowledge of CMOS processes and deep submicron process technologies. Proficiency in CMOS circuit design and layout methodology. Familiarity with analog mixed-signal simulation strategies. Understanding of JEDEC requirements for DDR interfaces and standards. Strong project management and leadership skills. Excellent written and verbal communication skills. Who You Are: A natural leader with the ability to inspire and guide a team. An excellent problem solver with a keen analytical mind. A collaborative team player who thrives in a cross-functional environment. A detail-oriented individual with a commitment to quality and efficiency. A proactive communicator who can convey complex technical information clearly.

* Collaborate with cross-function al teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs using industry-stand ard EDA tools. * Perform physical verification and design rule checks to ensure design integrity and manufacturabil ity. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensure the delivery of high-quality layout designs for PVT Sensor IP development, integral to SOC subsystems. * Enhance the manufacturabil ity and reliability of our silicon lifecycle monitoring solutions. * Drive innovation in layout design methodologies and best practices. * Collaborate effectively with circuit designers to meet design specifications and constraints. * Contribute to the overall success of the rapidly expanding PVT IP group. * Support Synopsys leadership in the market for process, voltage, temperature, current, and droop sensors. What You ll Need: * Bachelor s or master s degree in electrical engineering or a related field. * 5+ years of experience in A&MS layout design for integrated circuits. * Proficiency in industry-stand ard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. * Exceptional knowledge of layout design methods, techniques, and methodologies. * Experience with physical verification tools, such as Calibre or Assura. * Understanding of semiconductor process technologies and their impact on layout design. * Excellent problem-solvin g and systematic skills. * Ability to work effectively in a team-oriented environment. * Good communication and interpersonal skills.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. What You ll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after the post graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

Leading the development of next-generation DDR/HBM/UCIe IPs. Advising team members to meet schedules and resolve problems effectively. Taking on project leadership roles and contributing to complex project aspects. Developing and maintaining project schedules, ensuring timely delivery. Collaborating in cross-functional settings to drive project success. Demonstrating proficiency in design and verification processes. The Impact You Will Have: Driving innovation in next-generation DDR/HBM/UCIe IP development. Enhancing the performance and capabilities of our Silicon IP portfolio. Ensuring high-quality and efficient project execution. Mentoring and guiding team members to achieve their full potential. Contributing to the rapid integration of advanced technologies into SoCs. Helping Synopsys maintain its leadership in the semiconductor industry. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or a related field. 8+ years of experience in CMOS circuit design and layout methodology. In-depth understanding of analog/mixed-signal circuitry and ESD concepts. Familiarity with analog mixed-signal simulation strategies. Knowledge of JEDEC standards for DDR interfaces and ASIC design flow. Who You Are: Visionary leader with strong problem-solving skills. Excellent communicator with the ability to lead and mentor teams. Detail-oriented and proficient in project management. Adaptable and able to thrive in cross-functional settings. Committed to achieving high standards of product quality and efficiency

An experienced and passionate Layout Design Sr Engineer with a strong background in Analog and Mixed Signal Circuit Layout. You possess a deep understanding of semiconductor device physics and have hands-on experience in EDA tools for custom mixed signal layout flows. Your expertise in CMOS and FINFET technologies, coupled with your knowledge of CMOS fabrication technology, equips you to handle deep sub-micron effects and their impact on layout. You are self-directed, detail-oriented, and have excellent problem-solving and communication skills. Your enthusiasm for learning and exploring new layout techniques drives you to innovate and excel in your role. What You ll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You ll Need: Bachelors or masters degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus. Who You Are: Self-directed and detail-oriented. Excellent problem-solving skills. Strong communication skills. Passionate about learning and exploring new layout techniques

The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. K EY RESPONSIBLITIES : Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. P REFERRED EXPERIENCE : Years of experience 13+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills. Strong digital design knowledge. Exposure to UPF based low power RTL verification. Prior experience in leading a team is desirable. Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits. You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation. Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work. You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools. Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset. What You ll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.

Pre-silicon design simulations, and post silicon validation for the product. Perform simulation to silicon matching activities by running simulation and microprobing critical circuits to capture waveforms to compare back to simulations and analyze the results for improvement of the design. Work closely with the Design Teams on forward looking design features, innovations and circuit development activities. The Design characterization engineer will be responsible for performing product characterization and debugging (using Bench test equipment, microprobe, ATE, etc.) Determine design implications on manufacturability, test product features and debug early silicon and verify design features. Qualifications and Skills include: The preferred candidate needs to have Design / Product engineering background including circuit design, product characterization and debugging on Memory Working knowledge in the following areas: Circuit / logic design, Semiconductor device physics is a plus. Working knowledge of the following area is a plus: Bench test equipment (O-Scope, Logic Analyzers). Experience with Teradyne Magnum Test program, C++, Python, Statistics. Effective oral and written communication with strong analytical, problem solving, and project management skills

Verification of Analog and mixed signal circuits. Generation of a Full chip mixed signal simulation environment where analog, digital and FW co-exist. Schematic/behavioral model generation of certain blocks to make FC simulation feasible/efficient Device level electrical rule checks - SOA, snapback, sfb etc Static and dynamic simulations to identify the leakage paths SPF extraction and fanout, coupling checks Power cycling simulations - PL and Brown out events Chip level user mode simulations correlating analog subsystems, logic and FW algorithms Design data sheet review and generation of verification plan

We are seeking a skilled Analog Layout Engineer to join our team at Nsemi. In this role, you ll be responsible for designing and optimizing analog and mixed-signal IC layouts, ensuring high performance and reliability. Your expertise will involve layout creation, verification, and adherence to design rules and specifications. Ideal candidates will have strong experience with analog circuit design, proficient use of layout tools, and a keen eye for detail. Join us to work on cutting-edge projects and contribute to the advancement of semiconductor technology. Qualification Required: Typically requires minimum of 3+ years of experience in Analog Circuit Design Bachelors / Master Degree in E&E and E&C Strong communication & team work skills Roles And Responsibilities: Expert in Power Management including hands-on DC-DC Converter, other precision analog circuits like operational amplifiers, Band-gap references, POR, Current Limit circuits, LDO regulators, comparators, oscillators etc. Experience in transceiver design for high speed interface such as Serdes, highspeed,DDR, HBM, PCIe, USB3, JESD204, Experience in transceiver design for high speed interface such as PLL,CTLE, DFE, CDR,PCIe, USB3, JESD204 Candidate should have taken atleast one block from circuit design and should be guide layout engineers for closure. Strong competency in small signal analysis and various frequency compensation techniques. Understanding of chip level ESD/LU requirements. Top-level integration, Block-level verification across PVT, Statistical Mismatch & mixed signal Verification. Hands-on working with Tools - Virtuoso/Tanner for schematic/model design & verification. Work closely with the Layout engineer to get optimized IP layout. This involves managing IP planning. Experience with Silicon validation and debug process. Planning, managing full-chip execution with team. Advantage if candidate has experience with high-current designs and/or multi-phase operation switching regulators

Gain hands-on experience in RFIC design, working with advanced EDA tools. This internship offers real-world experience and learning from industry experts to enhance your skills. Network and build your professional portfolio.

About The Role Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsB.E/ B.Tech Electronics/Electrical/VLSI Design Engineering with 3+ years of relevant experience in Analog and IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, LVDS etc.Preferred Qualifications:Analog Device and Metal Layout FundamentalsAnalog/Mixed Signal FundamentalsReliability Verification.Cadence Virtuoso Layout Suite Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Analog Mixed Signal Layout Location: Bangalore, Hyderabad, Noida Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Experience (years) : 3 - 7 Years Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Description: Job Title: Memory Circuit Design Verification Engineer Memory Circuit Design Verification Engineer Description As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. Responsibilities Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Experience Level 3-7+ years Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

About Astrogate Labs Astrogate Labs is a space-technology start-up based in Bengaluru, building core technologies in laser communication terminals and networks for small-satellites. Astrogate Labs aims to simplify, reduce cost of communication, and enable satellites send more data to ground. We have developed one of the industry s smallest optical communication terminals targeted for small satellite use, further scaling our products and aiming for our first satellite mission. We aim to revolutionize satellite communications and support the growing satellite downlink needs with a network of optical ground stations and in-space relays using the technologies developed in-house. We are looking for bright and passionate folks like you to join our exceptional team. Qualification: BE/BTECH/ME/MTECH in Electronics & Communication or Electrical engineering or any other related field with 2+ years of relevant experience. Job Responsibilities: Design Analog, Digital and Mixed Signal boards. Work in end-to-end design and bring up of boards., i.e., from understanding the requirements, selecting the appropriate components, schematic capture, PCB layout and design, sending out boards for manufacturing and testing of boards. Simulate various circuits in simulation software such as Tina-TI and LTSpice and others. Involved in handling Inventory, Version Control of projects etc Involved in soldering SMD components and debugging/reworking on the boards. Involved in selection of components, distributers, and manufacturers. Required Skills/Experience: 2+ Years experience in Electronics Design field Understanding of Analog and Digital Electronics 2+ Years of working with any ECAD tools Worked on multiple end-to-end boards. Hardware debug experience, including familiarity with tools such as the oscilloscopes, logic analysers, and signal generators. Must be an independent thinker and motivated to work within a multidisciplinary team. Desired Skills/Experience Prior aerospace/optical communications related experience is an added advantage. Experience with Embedded C and Free-RTOS Experience with designing High-Speed Mixed signal boards Knowledge of various EMI/EMC standards used in Industry. Benefits you get working with us: Association & supervision by industry experts and senior members. Other early-stage company benefits including ESOPs Team oriented work culture for the development of extraordinary space products

Staff Engineer, Analog Location: Bangalore Key Responsibilities Developing low-power, high-performance analog circuits, including OpAmp, Comparators, Bandgap References, LDOs, Capless LDO, ADCs, DACs, PLL, DLL, Switching Regulator, High Speed IOs, DDR in advanced process nodes. Defining circuit implementation architecture based on specifications, creating transistor-level designs, and collaborating with analog layout designers for optimization. Creating and maintaining documentation for designs, including specifications, test plans, usage guidelines, and limitations. Collaborating with system architects, the analog design team, and the DV (Design Verification) team for DV modeling and digital top verification. Mentoring junior designers and sharing best practices to enhance design performance and productivity. Requirements : B. Tech /BE/ME/M Tech in Electronics/Electrical Engineering or related fields with 5+ years of relevant hands-on experience. Strong experience in analog and mixed-signal circuit design and/or architecture. Experience with advanced process/FinFET is a plus. Understanding of device basics and physics, with an understanding of the following: High speed Driver and Receiver designs, PLL design with solid system understanding Hands-on experience of Sub block design of Current mirrors, bandgap reference, Opamp, amplifiers with small-signal analysis of several topologies. Experience in ADC/DAC/Regulator or High Speed SerDes circuit design Good knowledge of devices, circuits, and EDA tools (schematic, layout, simulator, RC extraction, etc.), considering trade-offs among performance, power consumption, die area, and reliability. Basic knowledge of the following layouts: antenna checks, antenna failure, latchup issues, ESD constraints, and layout rules, ERC related checks, matching, cross talk, coupling, shielding, guard ring usage, LEF generation, .lib characterization, extraction setup, DRC LVS runs switch knowledge, IR drop requirements, EM issues, parasitic matching, parasitic reduction techniques, and static and dynamic IR analysis Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Excellent written and verbal communication skills.

Title: Memory Layout Engineer (SRAM/NVM) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for SRAM/ROM memory circuits, which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Your Job: The development of product grade SRAM memory IP s covering the following phases: Layout Design of SRAM Memory IPs Layout checks like LVS,DRC,DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team-player taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of the silicon bring up and characterization Required Qualifications : Bachelor s degree with 8+ years or master s degree with 6+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Memory and Custom Mixed-signal layouts at one or several of the following areas: Memory Layout design and NVM architecture & concepts Experience in NVM memory layout, SRAM layouts and Testchip integration will be an added advantage Hands on knowledge of state-of-the-art memory or analog layout flows Familiarity with Custom digital layout (i.e high speed logic paths) Proficient in Basic concepts of matching, shielding, power optimization and track planning Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Knowledge of layout effects (like matching, proximity effects etc) Basic understanding of fabrication steps and flow. General analog mixed-signal design concepts Circuit design, Reliability analysis, Statistical analysis of circuits Good understanding of CDL netlist and circuit hierarchy definition Tiler / compiler concepts, design layout compatible for tiler approach and verify Top level power routing and metal stack arrangement Preferred Qualifications: In depth familiarity with layout of analog and mixed signal CMOS circuits Programming experience applicable to design flow automation tasks The capability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28/14nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong debugging, analytical and trouble shooting skills Strong written and verbal communication skills in English are a must. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Title: Memory Layout Engineer (SRAM/NVM) About GlobalFoundries Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for SRAM/ROM memory circuits, which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Your Job: The development of product grade SRAM memory IP s covering the following phases: Layout Design of SRAM Memory IPs Layout checks like LVS,DRC,DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team-player taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of the silicon bring up and characterization Required Qualifications : Bachelor s degree with 8+ years or master s degree with 6+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Memory and Custom Mixed-signal layouts at one or several of the following areas: Memory Layout design and NVM architecture & concepts Experience in NVM memory layout, SRAM layouts and Testchip integration will be an added advantage Hands on knowledge of state-of-the-art memory or analog layout flows Familiarity with Custom digital layout (i.e high speed logic paths) Proficient in Basic concepts of matching, shielding, power optimization and track planning Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Knowledge of layout effects (like matching, proximity effects etc) Basic understanding of fabrication steps and flow. General analog mixed-signal design concepts Circuit design, Reliability analysis, Statistical analysis of circuits Good understanding of CDL netlist and circuit hierarchy definition Tiler / compiler concepts, design layout compatible for tiler approach and verify Top level power routing and metal stack arrangement Preferred Qualifications: In depth familiarity with layout of analog and mixed signal CMOS circuits Programming experience applicable to design flow automation tasks The capability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28/14nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong debugging, analytical and trouble shooting skills Strong written and verbal communication skills in English are a must. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

> If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 73553 Job Description We are a passionate and dedicated team of world-class analog, mixed-signal and digital design and verification engineers committed to building the next generation of SOCs. This position is for an experienced and equally passionate analog and mixed-signal engineer interested in excellent personal and professional growth opportunities. Your role: You will: Bring state of the art Analog and Mixed Signal IP and products to market. Provide guidance and oversee design and verification, systems, algorithms, etc. to meet product requirements . Interface with Analog and Digital, RF, DV engineers and module design teams to create the detailed specification, report design progress, and to collect, track, and resolve any performance and circuit design issues. Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Job Segment: Design Engineer, Network, Telecom, Telecommunications, Engineer, Engineering, Technology

• EXP. of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX. • Analog circuit in PMIC domain: Design of Voltage/Current references, Amplifiers, Comparators, Filters & Voltage sensors, Oscillators, Voltage clamps. Required Candidate profile • EXP on High Speed SERDES/ Memory Circuits is PLUS • Exposure to cutting edge technology nodes like FinFets is PLUS • Hands-On atleast 2/ 3 of Blocks • Strong Analog Design Fundamentals