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Analog Devices
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Staff Digital Mixed Signal (DMS) Design Verification Engineer

Staff Digital Mixed Signal (DMS) Design Verification Engineer

Analog Devices

4 - 9 years

15 - 19 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

automation mixed signal analog healthcare perl silicon dms licensing analog design python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Analog Devices is seeking Digital Mixed Signal Design Verification Engineer for a Staff level role, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.

About the Role

Key members of design verification team, which has both digital mixed-signal and digital design verification engineers . T he candidate will be responsible for formulating verification strategies and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both D BU and ADI. The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible .

Requirements

B.Tech / M.Tech with 8 + years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (DMS DV ) .

Good understanding of analog design concepts and mixed signal design architectures . E xposure to products that integrate a wide variety of A nalog / M ixed- S ignal building blocks such as P ower M anagement, ADC s, DACs, PLL, ban d gap references, oscillators , S er D es etc. and related digital control and signal processing .

Demonstrated e xperience of verification plan , verification environment development and verification/ debug of complex mixed signal products at block & chip-top level s in DMS set-up .

Experience of co-simulations with analog model s and digital RTL/ Gate+SDFs .

Proven experience in closing the verification of analog macro s and its interaction with digital components using industry standard metrics is a must .

Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe .

Proficiency in the technical & interdependency management of DMS DV team execution is a must .

Quick to adopt new technologies with good problem-solving skills.

Self-motivated and enthusiastic.

Responsibilities& Key Skill Sets

Come up with verification strategy for a product after going through product requirements and design specifications .

Create SV Real Number M odels for analog /mixed-signal blocks for subsystem & chip-top verification . Validate models against actual design .

Familiarity with Analog/Mixed-Signal/RF design architectures and debug experience with Xcelium , DMSO, S chematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision and Verisiu m .

Experience with SV/UVM (agent creation, env building, score-boarding, RAL etc.).

Create verification plan s , build DMS verification environment for subsystem & chip-top verification , develop self-checking testcases .

Tracking verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager .

Verification closure using vplan mapping, code & functional coverage .

Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV , PTE etc. ) for first pass silicon .

S upport DFT & test and characterization teams in validating key scenario s in pre-silicon environment for faster post-silicon bench bring-up and validation .

Work on the Flow/KPI improvement initiatives or design verification methodologies

Automation with scripting languages: Python/Perl/ Shell etc.

Formal Verification using Jasper .

Expected to be the overall D MS DV lead of a proje ct.

Mentor fresh graduates and junior engineers

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Staff Digital Mixed Signal (DMS) Design Verification Engineer