Design Verification Engineer

We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards.

Key Responsibilities:

1. Ethernet Protocol Expertise

• Demonstrate expertise in Ethernet standards, encompassing 100G to 800G.
• In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA).
• Proficiency in PTP 1588 standard and various Ethernet frame types.
• Competence in packet insertion/extraction techniques.
• (Additional knowledge of AXI protocol would be considered an advantage)

1. UVM/SV Proficiency

• Showcase strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).

1. Architectural Skills

• Proven ability to architect, build, and maintain a comprehensive verification stack.

1. Test Development

• Extensive experience in developing a set of regression tests for verification purposes.

Qualifications:

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 to 12 years of relevant industry experience in IP and SOC verification.
• Strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Excellent understanding of Ethernet protocols, ranging from 100G to 800G.
• Proficiency in PTP 1588 standard and various Ethernet frame types.
• Experience with packet insertion/extraction techniques.
• Knowledge of AXI protocol (preferred).
• Proven ability to architect, build, and maintain verification stacks.
• Demonstrated expertise in developing a comprehensive set of regression tests.