6 Axi Protocol Jobs

Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed test plan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Strong knowledge in IP/SOC design methodologies. Power aware verification expertise using UPF (Unified Power Format) Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog Mentoring juniors and enhancing their skill set Must have strong knowledge of AMBA AHB/AXI protocol Working knowledge on code coverage, functional coverage, Lint, CDC etc IP development and coding using standard coding guide lines knowledge Excellent communication skills. Must be able to particpate lead in global meetings Soft skills to be able to work in a cross functional international team digital and software design engineers Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme PREFERRED EXPERIENCE: 6+ Years for experience Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Experience with power-aware verification methodologies and UPF Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.

Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed test plan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise emulation / prototyping using Cadence / Synopsys tool flows Expertise in Palladium / Protium / HAPS / Zebu tools Expertise in System Verilog & Verilog language semantics and compilation flows Expertise on AXI protocol Good Knowledge on SOC architecture

As a Design Verification Lead/Manager with 8-18 years of experience in IP/Subsystem level Verification, you will be responsible for overseeing the verification process. You should have a strong background in verifying PCIe protocol, including Gen4, Gen5, and Gen6. In addition, you should possess good knowledge of PCIe transaction layer, routing, reset flows, as well as experience with AXI protocol and NOC subsystem verification. Your role will require solid SV-UVM knowledge and hands-on experience in testbench development. Strong debugging skills are essential for this position. Knowledge of performance verification would be considered a plus. As a leader, you will be expected to manage a team of 8-10 members and take technical ownership of the project. Your ability to lead and guide the team effectively will be crucial for the successful completion of the verification tasks.,

As an ideal candidate for this role, you should possess 3-5 years of experience in emulation/prototyping utilizing Cadence tool flows such as Palladium and Protium. Your expertise should extend to having a working knowledge of System Verilog and Verilog language semantics, along with familiarity with compilation flows associated with these languages. A solid understanding of SOC architecture and the AXI protocol is essential for this position. Your ability to comprehend and work effectively with SOC architectures and AXI protocol will be crucial to your success in this role. Moreover, strong communication skills and the capacity for effective team collaboration are highly valued. Your ability to communicate effectively and collaborate efficiently with team members will contribute significantly to the overall success of the projects you will be involved in.,