Design Verification Engineer

We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory).

Key Responsibilities:

1. IP and SOC Verification

• Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits.

1. SystemVerilog (SV) and UVM Proficiency

• Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes.

1. CDP, GDP, DFT DV Expertise

• Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies.
• Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM.

Qualifications:

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 to 12 years of relevant industry experience in IP and SOC verification.
• Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM.