1105 Dft Jobs - Page 14

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 2 years of experience with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. Experience scripting in Python or Perl or other related language. Experience with silicon process and technology nodes for high speed and low power consumption. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Develop test patterns that optimally tests the logic/Memory/Analog Macro under test. Work with internal cross-functional teams, external silicon partners, Product Engineering team, and Intellectual Property (IP) vendors to support structural validation and parametrically characterize the Silicon. Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of subsystems. Preferred qualifications: Experience in SoC designs and integration flows. Experience with scripting languages (e.g., Python or Perl). Knowledge of high performance and low power design techniques. Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate and improve traffic in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and logic solutions, and evaluate design options with complexity, performance, power and area in mind. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Own microarchitecture and implementation of subsystems in the data center domain. Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Perform Quality check flows like Lint, CDC, RDC, VCLP. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and subsystems. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with performance, power, and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design and more to specify and deliver high quality designs for next generation data center accelerators. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Own implementation of IPs and subsystems. Work with Architecture and Design Leads to understand micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance, and Area improvements for the domains.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.

Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 5 years of experience in DFT specification definition architecture and insertion. 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent). Experience with ASIC DFT synthesis, STA, simulation, and verification flow. Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.). Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST). Experience in SoC cycles, including silicon bring-up and silicon debug activities. Experience in fault modeling. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. Demonstrate ownership from DFT logic, pre-silicon verification, to co-work with test engineers post silicon. Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks. Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces. Document DFT architecture and test sequences, including boot-up sequence associated with test pins. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support post-silicon test team.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT/DFD flows and methodologies. Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow. Experience developing DFT specifications and driving DFT architecture. Preferred qualifications: Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging. Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD. Experience with STA constraints development and analysis for DFT modes and SDF simulations. Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues Knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL). About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define Design for Excellence (DFX) specifications and develop flows and methodologies for new technology node implementation. Implement/Integrate and verify Design for Testing (DFT) logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, Test Access Port (TAP) controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns. Participate in post-silicon activity like bring up, diagnostics and characterization. Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.

Minimum qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test including silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. Experience with ATPG, Low Value (LV), Built-in self test (BIST) or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications: Experience with a programming language like Perl with Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC) and DFT timing and Static Timing Analysis (STA). Knowledge of performance design DFT techniques. Knowledge of the end to end flows in Design, Verification, DFT and Partner Domains (PD). Ability to scale DFT. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work on a team of Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. Write a Pattern delivery using Automatic Test Pattern Generation (ATPG). Work with Silicon bring-up. Work on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug and deliver debug patterns. Perform Silicon data analysis.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design integration. Experience in Verilog or Systemverilog coding. Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features. Interact closely with architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for Sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Principal Physical Design Engineer in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: Ampere Computing is seeking a highly skilled engineer to join our physical design team with a focus on both CPU/GPU physical design and interconnect integration/implementation for CPU and GPU products. This role requires deep expertise in high-speed and power efficient physical design and methodologies with hands-on experience implementing CPU/GPU & interconnect networks to deliver robust, high-performance silicon solutions. You will collaborate closely with Architects, RTL designers, packaging team, and timing, power & DFT teams to ensure robust, high-performance designs that meet stringent timing, power, and area requirements. Interconnect floor planning iterations, partitioning, pin-placement, wire planning, clock distribution network. Working with Architecture, RTL and timing teams for optimal floorplan from system performance point of view. Implement power and clock domain crossing with UPF and timing methodologies. Converge timing on high speed interface with appropriate methods of clock balancing and skewing. Lead and execute physical design tasks for CPU/GPU blocks including floor planning, placement, clock tree synthesis, routing, and optimization. Collaborate with RTL designers and timing engineers to achieve timing closure, power targets, and area goals. Perform physical verification and signoff checks ensuring design compliance with foundry rules and design specifications. Analyze and resolve physical design issues such as congestion, timing violations, and signal integrity challenges. Develop scripts and automation flows to improve design efficiency and quality. Address interconnect-related challenges such as crosstalk, IR drop, electromigration, and noise. Document design methodologies, best practices, and integration guidelines specific to Ampere s CPU/GPU physical design flows. Collaborate and work with cross geo teams in India & Vietnam About you: M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Experience in high performance/low power physical design, preferably with a focus on CPU and/or GPU architectures. Proven expertise in both CPU / High performance physical design and interconnect integration/implementation. Solid understanding of timing analysis, signal integrity, power integrity, electromigration, and advanced process technologies (7nm, 5nm, or below). Deep understanding of semiconductor device physics, interconnect materials, and advanced process technologies (7nm, 5nm, or below). Strong proficiency with EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, and parasitic extraction tools (StarRC, Quantus). Experience with scripting languages (Tcl, Python) for automation and tool customization. Excellent problem-solving skills and ability to work effectively in cross-functional teams. Effective communication skills to collaborate with design, verification, and manufacturing teams. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Principal Physical Design Engineer in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: Ampere Computing is seeking a highly skilled engineer to join our physical design team with a focus on both CPU/GPU physical design and interconnect integration/implementation for CPU and GPU products. This role requires deep expertise in high-speed and power efficient physical design and methodologies with hands-on experience implementing CPU/GPU & interconnect networks to deliver robust, high-performance silicon solutions. You will collaborate closely with Architects, RTL designers, packaging team, and timing, power & DFT teams to ensure robust, high-performance designs that meet stringent timing, power, and area requirements. Interconnect floor planning iterations, partitioning, pin-placement, wire planning, clock distribution network. Working with Architecture, RTL and timing teams for optimal floorplan from system performance point of view. Implement power and clock domain crossing with UPF and timing methodologies. Converge timing on high speed interface with appropriate methods of clock balancing and skewing. Lead and execute physical design tasks for CPU/GPU blocks including floor planning, placement, clock tree synthesis, routing, and optimization. Collaborate with RTL designers and timing engineers to achieve timing closure, power targets, and area goals. Perform physical verification and signoff checks ensuring design compliance with foundry rules and design specifications. Analyze and resolve physical design issues such as congestion, timing violations, and signal integrity challenges. Develop scripts and automation flows to improve design efficiency and quality. Address interconnect-related challenges such as crosstalk, IR drop, electromigration, and noise. Document design methodologies, best practices, and integration guidelines specific to Ampere s CPU/GPU physical design flows. Collaborate and work with cross geo teams in India & Vietnam About you: M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Experience in high performance/low power physical design, preferably with a focus on CPU and/or GPU architectures. Proven expertise in both CPU / High performance physical design and interconnect integration/implementation. Solid understanding of timing analysis, signal integrity, power integrity, electromigration, and advanced process technologies (7nm, 5nm, or below). Deep understanding of semiconductor device physics, interconnect materials, and advanced process technologies (7nm, 5nm, or below). Strong proficiency with EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, and parasitic extraction tools (StarRC, Quantus). Experience with scripting languages (Tcl, Python) for automation and tool customization. Excellent problem-solving skills and ability to work effectively in cross-functional teams. Effective communication skills to collaborate with design, verification, and manufacturing teams. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Position : Digital Head Semiconductor BU (Confidential Search) Location: Hyderabad / Chennai/Bangalore Client: 20+ year-old leading semiconductor/VLSI design services company delivering SoC/ASIC design, verification, physical design, DFT, embedded systems, and post-silicon validation for Tier-1 global clients. We are partnering on a confidential leadership mandate for a Digital Head to drive digital strategy, delivery excellence, and innovation across global semiconductor programs. Key Responsibilities: Lead and grow multi-disciplinary teams Semiconductor Digital Design (RTL, PD, DV, DFT) Own delivery of complex SoC/ASIC programs across global accounts Define capability roadmap, drive innovation in AI/ML + EDA Partner with sales, pre-sales, and engineering to shape go-to-market Ideal Profile: 15–25 years in semiconductor design, with 5+ years in senior leadership B.E./B.Tech in ECE/VLSI; M.Tech/MS preferred with 20+ years of experience Proven track record in RTL, DV, DFT, and EDA toolchains Must have Leadership experience Candidates currently or previously working in these companies would likely have relevant experience) Semiconductor Product/Design Companies: Engineering Services/Design Services Companies: EDA & IP Companies If you meet 80% of the requirement contact : bdm@intellisearchonline.net M 9341626895(whatsapp)

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks. What you ll be doing: Own micro-architecture and RTL development of design modules. Micro-architect features to meet performance, power and area requirements. Work with HW architects to define critical features. Collaborate with verification teams to verify the correctness of implemented features. Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 5+ years of design experience. Experience in RTL design of complex design units for at least two or three projects. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Leadership experience in leading small 2-3 member teams. Good interpersonal skills and ability & desire to work as a part of a team. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. #LI-Hybrid

Key Responsibilities: Drive sales strategy and revenue growth in VLSI and IC design services Identify and win new business opportunities (new logos & expanded accounts) Engage with R&D and engineering leadership at Tier-1 semiconductor firms Build and maintain strong client relationships through consultative selling Collaborate with presales, delivery, and hiring teams to fulfill project needs Create strong sales pipeline through proactive networking and outreach Mentor and lead a small, high-performing sales team Provide input on solution strategy, proposals, SoW, and MSA reviews Must-Have Skills: Proven experience in IC/VLSI Design Services sales Strong connects with top semiconductor firms (e.g., AMD, Qualcomm, Micron) Understanding of Silicon Engineering value chain (Frontend, Backend, Post-Silicon) Familiarity with RTL to GDSII, STA, DFT, Verilog, UVM Excellent communication, negotiation, and client handling skills Good-to-Have Skills: Hands-on background in VLSI design, verification, or validation Experience building VLSI service offerings, partnerships, and go-to-market plans Awareness of market trends and competitor strategies in semiconductors Ability to guide and grow business development or sales teams

Key Responsibilities: Define and lead VLSI back-end services strategy and offerings Build and scale high-performing VLSI engineering teams (300+ roadmap) Engage with semiconductor clients for technical discussions and project wins Oversee delivery of back-end services including physical design, STA, DFT, timing/power analysis Collaborate with sales, presales, and partner ecosystem to drive business growth Mentor engineers and ensure alignment to latest tech trends and client needs Lead proposal creation, solution demos, and client engagement at senior levels Must-Have Skills: Strong experience in VLSI/ASIC back-end engineering Physical design, timing closure, DFT, power/performance optimization Expertise in EDA tools (Synopsys, Cadence, Siemens) Verilog, LEF/DEF/SPEF formats Excellent leadership, communication & stakeholder management Good-to-Have Skills: Proficiency in scripting (Python, Perl, Tcl) Experience with advanced node technologies (7nm, 5nm, etc.) Exposure to ASIC-package co-design Strong industry connects (EDA vendors, foundries, Tier-1 chipmakers) Strategy planning, SoW/MSA reviews, innovation initiatives

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Job Description: Senior Staff Engineer We are looking for a technical leader to drive the DFT aspects of high-performance compute MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Qualifications Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can–do attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Job Description: Staff Engineer We are looking for a technical leader to drive the DFT aspects of high-performance compute MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Qualifications Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 8 years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can–do attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Position Vacant : Hardware Design Engineer – Motor Control Organization Name : BLAER MOTORS PRIVATE LIMITED Company Profile: Established in 2014, Blaer Motors Private Limited is a technology-based company with over 8+ years of domain expertise in developing control systems for XeV drivetrains solution (Hybrid Electric Drivetrains & Battery Electric Drivetrains). We offer First in Segment solutions of Smart Motor Controller Unit (up to 10kW), Vehicle Control units for 2W/3W (both Hybrid Vehicle Control Units & Electric Vehicle Control Unit). Qualification B.E. /B. Tech. / M. Sc. / M. Tech. Experience 3 to 6 Years of experience Required Skill Set: 1. Bachelor's or Master's degree in Electrical Engineering, ElectronicsEngineering, or a related field. 2. Extensive experience in embedded hardware design, with a focus on motor control systems for electric vehicles. 3. Proficient in schematic capture and PCB design tools (e.g., Altium Designer, Cadence Allegro), and familiar with design for manufacturing (DFM) and design for testing (DFT) principles. 4. Solid understanding of motor control theory, power electronics, and semiconductor devices. 5. Experience in selecting and integrating motor control ICs, gate drivers, sensors, and other relevant components. 6. Knowledge of automotive industry standards, safety regulations, and functional safety (ISO 26262) requirements. 7. Proficiency in simulation and analysis tools for hardware design validation (e.g., SPICE, electromagnetic simulation tools). 8. Strong problem-solving skills and the ability to debug and troubleshoot hardware-related issues. 9. Excellent communication skills and the ability to work effectively in a collaborative team environment. 10. Experience with EV-specific challenges, such as high-voltage systems, thermal management, and EMI/EMC mitigation, is a plus. Join our team and contribute to the exciting and rapidly evolving field of electric vehicle technology Relevant Industry : Automotive T1 Job Description / Responsibilities 1. Design and develop hardware solutions for motor controller systems, including schematic capture, component selection, and PCB layout, while ensuringcompliance with industry standards, safety regulations, and system reliability requirements. 2. Conduct feasibility studies and performance evaluations of motor control hardware designs, considering factors such as power efficiency, thermal management, electromagnetic compatibility (EMC), and manufacturability. 3. Work closely with suppliers and manufacturers to source components and materials, ensuring timely delivery and quality control throughout the production process. 4. Conduct thorough testing and validation of motor control hardware, including functional testing, performance analysis, and reliability testing, to ensure optimal system performance and durability. 5. Collaborate with firmware engineers to optimize hardware-firmware interaction and troubleshoot any hardware-related issues during integration and testing phases. 6. Support the product development lifecycle, including prototyping, design verification, certification, and production ramp-up activities. Job Location Chennai, Tamil Nadu. Job Type: Full-time Pay: From ₹60,000.00 per month Benefits: Health insurance Provident Fund Schedule: Day shift Monday to Friday Supplemental Pay: Commission pay Yearly bonus Ability to commute/relocate: Chennai, Tamil Nadu: Reliably commute or planning to relocate before starting work (Preferred) Application Question(s): What is your current CTC Notice Period? Experience: Motor control unit design: 3 years (Required) Work Location: In person

Dear Candidates, Great Opportunity ! Hiring for #Transport Modelling Experience - Min 7 years Location - Banglore Qualification - B. Tech / B.E. #SATURN Salary - No bar for Right Candidate Job Description :- Your responsibilities will include but are not limited to the following: Working on highway and strategic multi-modal modelling projects. Involvement in projects including survey programmes, model development, calibration, validation, demand forecasting and economic appraisal. Checking outputs for compliance with quality requirements and industry best practice. Provide key inputs to the development of business cases and scheme assessments. Liaise with clients and other project stakeholders. Contribute to business development activities including proposal preparation. Person Specification As a Transport Modeller, you will be committed to providing high quality, affordable and innovative solutions. Ideally you will already have experience working in a Global Delivery teams facing UK clients. To carry out the responsibilities we will require: Numerate degree (or equivalent) ideally in a transport related discipline. Master degree is advantageous but not essential. 8-12 Years of experience in Transport Modelling. Good experience using SATURN modelling software. An understanding of the requirements of the UK DfT’s TAG guidance and evidence of implementation on projects. Experience of using UK DfT software such as DIADEM, TUBA, WITA. Experience of survey design and data analysis skills. An understanding of variable demand modelling and forecasting. The following would also be desirable but not essential: Expertise in Geographic Information System (GIS). Experience in the use of other software such as VISUM, CUBE or EMME. Knowledge of microsimulation software such as VISSIM, PARAMICS, AIMSUN. Coding/scripting/database skills. Interested Candidate can share cv to g.jugeesha@rightadvisors.com 9667275685

Your Job To help develop / support new and existing PCB that meets or exceeds customer expectations. Provide guidance for new PCB development to generate revenue and growth for Business Unit. To grow his/her team members in becoming high performers. What You Will Do Design and develop printed circuit boards (PCBs), including schematic capture, multilayer layout, and DFM/DFA best practices. Ensure electronic designs are optimized for manufacturing using both wave soldering and pick-and-place assembly processes. Oversee and support the full manufacturing process, including SMT, THT, and manual assembly operations. Identify and Resolve PCB assembly issues, including solder defects, component placement errors, and thermal concerns and add improvement plans to address soldering issues during the design phase itself. Lead prototype builds and transition designs into volume production, ensuring cost-effectiveness and reliability. Collaborate with contract manufacturers and in-house teams for prototyping, testing, and transitioning designs into volume production. Manage BOMs, component sourcing, and work closely with supply chain teams for lead time and availability optimization. Maintain accurate documentation for designs, assembly processes. Who You Are (Basic Qualifications) B.E./B.Tech Degree in Electrical or Electronics Engineering PCB design using tools such as Cadence and Altium Designer. Hands-on experience with wave soldering techniques and pick-and-place machines (e.g., Yamaha, Juki, Mycronic, etc.). Strong knowledge of SMT and THT assembly processes and IPC standards (e.g., IPC-A-610). Familiarity with DFM, DFA, and DFT principles. Proven ability to collaborate with EMS providers and in-house manufacturing teams. What Will Put You Ahead Technical leadership experience in PCB Design At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate's knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy. Who We Are {Insert company language from Company Boilerplate Language Guide} At Koch, employees are empowered to do what they do best to make life better. Learn how our business philosophy helps employees unleash their potential while creating value for themselves and the company. Additionally, everyone has individual work and personal needs. We seek to enable the best work environment that helps you and the business work together to produce superior results.

Job Description: Role & responsibilities Experience in Component Selection, schematic capture, library generation, routing rules creation, signal integrity optimization. Power Supply board layout designing with knowledge of signal Isolation and others Layout tools - Allegro, Altium, Mentor Graphics Expedition. Shall have worked on complex design involving RF/Analog and digital technology spanning multiple logic families. Shall have expertise in understanding the electrical (SI / Timing / EMI) aspects of the design shall be capable of providing solutions to the customers in this domain have complete knowledge of the PCB fabrication aspects including HDI, shall be conversant with the DFx needs of the industry should have the impetus to update the skill set of self and the team should provide the support for training of the team. Preferred candidate profile Layer Stackup Planning Familiar with 4+ Layer PCB Design Familiar with Flex PCB Design & Manufacturing Process. Sound Understanding PCB Design, Manufacturing and Testing process. Know about DfX (DFM, DFC, DFT, etc.) Sound knowledge about active and passive component selection. Good knowledge about PCB troubleshooting. Good Knowledge about IPC Standards like IPC2221. Good Command on PCB design tools like Altium, KiCad, OrCad, PADs, etc. Additional Skills (Good to Have) IPC2222 & IPC2223 IEC60601 Familiar with the Risk management process. Familiar with LED Driving Circuit Designing, Buck-Boost conversion topology. Should understanding of Routing single ended and differential track Familiar with Blind and Buried via and its impact on cost and Manufacturing. Perks and benefits A highly motivated, young and hardworking team. Fast growing company with a lot of opportunities to develop yourself. Awesome products and international clients to work with. Proper salary, holiday allowance, vacation days. Your work contributes to the health of the general public. Opportunities to travel the world.

Job Description Position Vacant : Hardware Design Engineer – Motor Control Organization Name : BLAER MOTORS PRIVATE LIMITED Company Profile: Established in 2014, Blaer Motors Private Limited is a technology-based company with over 8+ years of domain expertise in developing control systems for XeV drivetrains solution (Hybrid Electric Drivetrains & Battery Electric Drivetrains). We offer First in Segment solutions of Smart Motor Controller Unit (up to 10kW), Vehicle Control units for 2W/3W (both Hybrid Vehicle Control Units & Electric Vehicle Control Unit). Qualification B.E. /B. Tech. / M. Sc. / M. Tech. Experience 3 to 6 Years of experience Required Skill Set: 1. Bachelor's or Master's degree in Electrical Engineering, ElectronicsEngineering, or a related field. 2. Extensive experience in embedded hardware design, with a focus on motor control systems for electric vehicles. 3. Proficient in schematic capture and PCB design tools (e.g., Altium Designer, Cadence Allegro), and familiar with design for manufacturing (DFM) and design for testing (DFT) principles. 4. Solid understanding of motor control theory, power electronics, and semiconductor devices. 5. Experience in selecting and integrating motor control ICs, gate drivers, sensors, and other relevant components. 6. Knowledge of automotive industry standards, safety regulations, and functional safety (ISO 26262) requirements. 7. Proficiency in simulation and analysis tools for hardware design validation (e.g., SPICE, electromagnetic simulation tools). 8. Strong problem-solving skills and the ability to debug and troubleshoot hardware-related issues. 9. Excellent communication skills and the ability to work effectively in a collaborative team environment. 10. Experience with EV-specific challenges, such as high-voltage systems, thermal management, and EMI/EMC mitigation, is a plus. Join our team and contribute to the exciting and rapidly evolving field of electric vehicle technology Relevant Industry : Automotive T1 Job Description / Responsibilities 1. Design and develop hardware solutions for motor controller systems, including schematic capture, component selection, and PCB layout, while ensuringcompliance with industry standards, safety regulations, and system reliability requirements. 2. Conduct feasibility studies and performance evaluations of motor control hardware designs, considering factors such as power efficiency, thermal management, electromagnetic compatibility (EMC), and manufacturability. 3. Work closely with suppliers and manufacturers to source components and materials, ensuring timely delivery and quality control throughout the production process. 4. Conduct thorough testing and validation of motor control hardware, including functional testing, performance analysis, and reliability testing, to ensure optimal system performance and durability. 5. Collaborate with firmware engineers to optimize hardware-firmware interaction and troubleshoot any hardware-related issues during integration and testing phases. 6. Support the product development lifecycle, including prototyping, design verification, certification, and production ramp-up activities. Job Location Chennai, Tamil Nadu. Job Type: Full-time Pay: From ₹60,000.00 per month Benefits: Health insurance Provident Fund Schedule: Day shift Monday to Friday Supplemental Pay: Commission pay Yearly bonus Ability to commute/relocate: Chennai, Tamil Nadu: Reliably commute or planning to relocate before starting work (Preferred) Application Question(s): What is your current CTC Notice Period? Experience: Motor control unit design: 3 years (Required) Work Location: In person

Role & responsibilities Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production. Ensure Test Coverage Goals are met at SoC Level. Addressing test quality targets in DFT architecture and test pattern generation. Leading various aspects of Test architecture including MBIST, Scan & ATPG. Work with different functions like front-end design, verification and physical design to ensure production quality silicon. Specific Knowledge/Skills Master/Bachelors Degree in Electrical/Electronic Engineering. Experience of 6 to 10 Years in DFT with successful delivery of production quality chips. Senior SoC DFT engineers, with experiences in all aspects of DFT, including MBIST, scan & ATPG, logic BIST. Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design. Self-motivated. Excellent written and verbal communication skill. Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components. Should be a team player and willing to work with cross functional teams in issues resolution.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Job Description: Staff Engineer We are looking for a technical leader to drive the DFT aspects of high-performance compute MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Qualifications Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 8 years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can–do attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 4 to 7 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Skills & Experience MTech/BTech in EE/CS with 7+ years of ASIC design experience. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage. Understanding of protocols like AHB/AXI/ACE/CHI is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Hands on experience in Low power SoC design is required. Responsibilities Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules. Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. Hands on experience in constraint development and timing closure. UPF writing, power aware equivalence checks and low power checks. Support performance debugs and address performance bottle necks. Provide support to sub-system, SoC integration and chip level debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 8+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for complex Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions.