1105 Dft Jobs - Page 11

Create the future of e-health together with us by becoming an Interface Analyst As a pioneer in digital health our heart beats for the development and implementation of new technologies. Become part of a cooperative Agile Team working in the latest technologies Angular and .Net developing PC base, cloud base and mobile base solutions. For the next level of e-health evolution we are looking for creative minds who enjoy working with a variety of technologies, their own design freedom and professional development. Empowering employees to solve challenging problems with full support of your peers. What you can expect from us - An extensive group health and accidental insurance program. A safe digital application and a structured and streamlined onboarding process. Our progressive transportation model allows you to choose: You can either receive a self-transport allowance, or we can pick you up and drop you off on your way from or to the office. Subsidized meal facility. Fun at Work: tons of engagement activities and entertaining games for everyone to participate. Various career growth opportunities as well as a lucrative merit increment policy in a work environment where we promote Diversity, Equity, and Inclusion. Best HR practices along with an open-door policy to ensure a very employee friendly environment. A recession proof and secured workplace for our entire workforce. What you can do for us: You are responsible for building the next physician office experience and help build an amazing application used by healthcare providers and patients across the country If you want to make a difference for physicians, nurses and patients with the code you write, and not just work on the next chat app, this opportunity is for you. Your main duties will include working with vendors and customers to implement important interfaces in the realm of labs (ORM, ORU), PM (ADT, SIU and DFT) and completely custom ones depending on need You and the team will participate in all phases of design and development; from high level design, to defining the REST APIs; to writing the code and tests. The application is built with most of the UI implemented using Angular. There is a messaging layer between the Angular and C# code. The backend is a REST API implemented using ASP.NET Web API. As a member of the team, you will work with all these technologies. Your Qualifications: 2+ years developing software with any OOP language knowledge. For example, C#, Microsoft .NET, or .NET Core. SQL knowledge is a strong plus. Experience designing or working with REST APIs is a strong plus Good knowledge of HL7 standard (ADT, SIU, DFT, ORM, ORU and others) as well as working with an HL7 interface engine - (C#, Mirth, Core point) Flexible to work shift per client requirement. ConvincedSubmit your persuasive application now (including desired salary and earliest possible starting date). We create the future of e-health. Become part of a significant mission.

Job Requirements Engineer must possess 3+ Years of exp at SoC Verification. C/C++ understanding is must. DFT-DV understanding is mandatory.

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076998

As an Astera Labs Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs connectivity products that support the world s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams. Basic qualifications: Minimum of bachelor s degree in computer engineering/ electrical engineering, Masters preferred. Minimum 12+ years of experience in a semiconductor company as a DFT engineer Must be local or willing to relocate Required experience : Chip design, Verilog and System Verilog Verification, UVM methodology ATPG tools Scan insertion tools Gate-level simulations Static timing analysis Scripting (Perl/Tcl) Familiarity with ATE Hands-on expertise with commercial test generation tools for large complex designs Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression Experience running test compression software Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools Preferred experience: Experience with defining and implementing SOC level verification on large designs. Working with 93k Tester Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B. S. /M. S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3. 0 , and other high-speed interfaces. Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc. ), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable.

Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Bachelor or Master degree in Electronics 48 years of hands-on experience in VLSI DFT Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc. ) Good understanding of RTL design, synthesis, and timing closure Experience with silicon bring-up and production test support Excellent problem-solving and debugging skills Strong communication and teamwork abilities Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc. ) Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Good understanding of RTL design, synthesis, and timing closure

Job Requirements 1. Lead High Performance ARM Core Hardening Job Title: Lead Engineer ARM Core Hardening Location: BLR/Hyd Experience: 812 years Technology Node: 5nm/3nm/2nm FinFET/GAA Reports To: Director/Technical Manager SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster). Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy. Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff. Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization. Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture. Interface with foundry and EDA vendors for process tech enablement and tool issues. Technical Skills: Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache). Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem. Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS. Experience with UPF-based low power flows and Conformal Low Power (CLP) verification. Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement). Familiar with physical architecture trade-offs (voltage islands, power domains, channel management). Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores. Experience taping out at 5nm or lower is mandatory. --- 2. Engineer ARM Core Hardening Job Title: Physical Design Engineer ARM Core Hardening Location: BLR/Hyd Experience: 38 years Technology Node: 5nm/3nm/2nm FinFET/GAA Key Responsibilities: Implement physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic. Perform static timing analysis, IR/EM validation, and physical verification. Optimize for frequency, leakage, and area within power and thermal budgets. Support integration of hardened cores into SoC top-level environment. Technical Skills: Good understanding of ARM core architecture and pipeline structure. Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk). Experience in UPF flows, CPF/UPF constraints, and low-power verification tools. Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs. Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC. Familiar with scripting (TCL, Python, Perl) to automate flows and reports. Work Experience Lead High Performance ARM Core Hardening Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP. Worked with multi-core cluster hardening and coherent interconnects (e. g. , CMN-600). Experience with RTL-based performance modeling and correlation with implementation ARM Core Engineer: ARM POP usage experience. Previous tapeout at \u22647nm. Exposure to hierarchical and multi-voltage designs. Familiarity with advanced floorplanning constraints for multi-core clusters.

We are looking for a technical leader to drive the DFT aspects of high-performance compute MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149. 1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Qualifications Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools such Tessent, Genus, FC, VCS and Conformal/Formality etc. Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude, openness to new environment, people and culture. Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus. Ability to work independently and as part of a team. Mentor and guide junior engineers in DFT.

Post-Silicon ATE Lead to lead and manage post-silicon validation and production testing efforts using ATE platforms. This role requires strong technical expertise in silicon characterization, test development, and working closely with cross-functional teams including design, DFT, packaging, and product engineering. Own and lead post-silicon validation and ATE characterization for silicon devices (SoC/MCU/ASIC). Develop and debug ATE test programs for characterization, qualification, and production ramp-up. Collaborate with design and DFT teams to define test coverage and validation strategy. Analyze silicon test data to identify functional/parametric failures, yield issues, or corner case behaviours. Lead silicon debug and root cause analysis of test failures. Define and drive test cost optimization strategies (e. g. , multisite, parallel test, retest strategy). Work with OSATs and vendors for probe card, loadboard, and socket development. Define test limits, corner conditions, and environmental conditions (HTOL, AC/DC, ESD, etc. ). Support qualification testing (e. g. , HTOL, HAST, Temp Cycle) and drive correlation Qualifications B. E. / B. Tech or M. E. / M. Tech in Electronics, Electrical, or related field. 1 2+ years of experience in post-silicon validation and ATE development. Strong hands-on experience with ATE platforms (e. g. , Teradyne UltraFlex, Advantest 93K, NI STS). Solid understanding of mixed-signal, digital, and analog test methodologies. Experience with scripting (Python, Perl, and C) for automation and data analysis. Familiarity with lab equipment (oscilloscopes, source meters, BERTs, etc. ) for correlation and debug. Excellent problem-solving skills and ability to work across global teams.

Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations. Collaborate closely with product and software architects to define and refine SoC-level architecture Play a key role in shaping the microarchitecture of complex IP blocks and SoC subsystems Work closely with functional verification teams on test-plan development and reviews Collaborate with other functional teams including Design, Validation, DFT, physical design and emulation teams to achieve architectural goals and performance targets Provide support to functional validation teams in post silicon debug IP selection and make/buy decisions are a key factor for this role Qualifications Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus BTech/MTech in Electrical / Electronic / Computer / Hardware Engineering with experience of 12+ years Can do attitude, openness to new environment, people and culture Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency Experience with benchmarking IP/SoC performance and tuning IP/SoC architecture Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS etc. . ) is a plus

Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies. Prepare basic documentation and status reports as required. Bachelor degree in Electronics, Electrical, or related field. Basic understanding of digital design and DFT concepts. Familiarity with Verilog or VHDL is an advantage. Good analytical and communication skills Work Experience Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies.

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

About the project: The Government-funded project focuses on the development and demonstration of drone and allied technologies. With applications spanning various sectors, the initiative leverages advanced technologies and infrastructure. It aims to foster strong industry- academia collaborations to address real-world challenges and drive innovation. Comprehensive training programs are an integral component, ensuring awareness and proficiency in drone operations. Qualification and Key Skills Required: PhD in a relevant experience OR MTech / ME or equivalent with minimum 2 years of relevant experience OR BTech / BE or equivalent with minimum 4 years of relevant experience Experience with designing multilayer PCBs with proficiency in industry-standard PCB designing tools like Altium, OrCAD, Cadence etc Strong understanding of high-speed design principles, impedance control, and differential pair routing. Experience in RF design, signal routing and hands-on testing using sophisticated lab equipment like spectrum analyzer. Experience of designing power electronic boards like SMPS, DC-DC converters, filter circuitry. Familiarity with electronic circuit designing and testing, microcontroller based designs, sensor interfacing, communication buses SPI, I2C, UART, CAN etc. Knowledge of signal integrity simulation tools (e.g., HyperLynx) is a plus. Experience with EMI/EMC mitigation techniques and environmental robustness (vibration, temperature). Ability to debug hardware using oscilloscopes, logic analyzers, and other lab tools. Good soldering skills even with small pitch components. Job Profile: Design highly integrated embedded and RF boards used for drone flight controller systems. Design and simulate analog /digital circuits (e.g., power regulators, IMUs, barometers, microcontrollers, communication interfaces, etc.). Design multilayer PCBs with signal integrity, thermal, power distribution and EMI/EMC considerations. Collaborate with system architects and embedded engineers to define PCB requirements. Design for testability (DFT), and compliance with aerospace-grade standards. Work with fabricators and assembly vendors for prototyping and manufacturing. Integrate feedback from field tests into board revision cycles. Provide detailed technical documentation, including specifications, test reports, and user guides. Any other work assigned as per requirement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Post-Silicon ATE Lead to lead and manage post-silicon validation and production testing efforts using ATE platforms. This role requires strong technical expertise in silicon characterization, test development, and working closely with cross-functional teams including design, DFT, packaging, and product engineering. Own and lead post-silicon validation and ATE characterization for silicon devices (SoC/MCU/ASIC). Develop and debug ATE test programs for characterization, qualification, and production ramp-up. Collaborate with design and DFT teams to define test coverage and validation strategy. Analyze silicon test data to identify functional/parametric failures, yield issues, or corner case behaviours. Lead silicon debug and root cause analysis of test failures. Define and drive test cost optimization strategies (e.g., multisite, parallel test, retest strategy). Work with OSATs and vendors for probe card, loadboard, and socket development. Define test limits, corner conditions, and environmental conditions (HTOL, AC/DC, ESD, etc.). Support qualification testing (e.g., HTOL, HAST, Temp Cycle) and drive correlation Qualifications B.E./ B.Tech or M.E./ M.Tech in Electronics, Electrical, or related field. 12+ years of experience in post-silicon validation and ATE development. Strong hands-on experience with ATE platforms (e.g., Teradyne UltraFlex, Advantest 93K, NI STS). Solid understanding of mixed-signal, digital, and analog test methodologies. Experience with scripting (Python, Perl, and C) for automation and data analysis. Familiarity with lab equipment (oscilloscopes, source meters, BERTs, etc.) for correlation and debug. Excellent problem-solving skills and ability to work across global teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Requirements Engineer must possess 3+ Years of exp at SoC Verification. C/C++ understanding is must. DFT-DV understanding is mandatory.

Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and firmware scenarios in RTL and GLS. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Mentor junior verification engineers and review their work. Establish verification methodologies and best practices QUALIFICATIONS Minimum requirements: Minimum of 3-4 years of experience in Digital IP Sub-system/SOC DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Experience in one or many of the following: C based Digital DV, scripting (Python/Perl/Shell) knowledge, UVM/System Verilog, AMS/GLS/CPF/UPF based verification, Post silicon verification etc Preferred qualifications: Strong in digital design fundamentals, computer organization & architectures and bus protocols. A good understanding of analog functionality and exposure to analog IC design methods. Ability to solve problems using a systematic approach Excellent debugging skills with Verilog/VHDL designs Work experience on C based environment with ARM/DSP processor-based systems including power aware simulations is a plus. Experience in Motor control/ BLDC motor driver devices including commutation, sensorless control and feedback systems are an added advantage Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Effective communication skills to interact seamlessly with all stakeholders Ability to quickly ramp on new systems and processes Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com. Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. JOB INFO Job Identification 25002354 Job Category Engineering - Product Dev Posting Date 07/11/2025, 09:22 AM Degree Level Bachelor's Degree Locations BANG Bagmane Tech Park, Bangalore, 560093, IN ECL/GTC Required Yes

Job Title: Quality Control Engineer Company: Retail Detailz India Pvt Ltd Location: Bhandup, Mumbai, India Overview: We're looking for a meticulous Quality Control Engineer to join our team. Your role will involve ensuring the precision and excellence of our sheet metal products through rigorous inspection and adherence to quality standards. Your attention to detail and commitment to maintaining high-quality standards will be pivotal in our manufacturing processes. Responsibilities: 1. Quality Inspection and Testing: - Perform visual inspections and dimensional measurements to verify conformance to specifications. - Conduct non-destructive testing (NDT) techniques like ultrasonic testing and magnetic particle testing, DFT, Impact Test etc 2. Quality Assurance Procedures: - Develop and implement quality assurance procedures for various stages of manufacturing. - Ensure compliance with quality management system standards and customer requirements. 3. Root Cause Analysis: - Investigate quality issues and implement corrective actions to prevent recurrence. - Collaborate with cross-functional teams to address quality-related challenges. 4. Documentation and Reporting: - Maintain accurate records of inspection results and quality-related documentation. - Prepare quality reports and trend analysis reports for management review. 5. Supplier Quality Management: - Evaluate the quality of incoming raw materials and components through incoming inspection. - Work with procurement teams to address supplier quality issues. 6. Training and Development: - Provide training on quality control techniques and procedures to production teams. - Stay updated on industry best practices and technological advancements. Requirements: - Diploma / Bachelor's degree in Mechanical Engineering or a related field. - Previous experience in quality control in sheet metal manufacturing. - Strong knowledge of quality control principles and techniques. - Proficiency in interpreting engineering drawings and specifications. - Experience with quality management systems and quality tools. - Excellent analytical and problem-solving skills. - Effective communication and collaboration abilities. - Detail-oriented mindset and ability to work independently. Job Type: Full-time Pay: ₹25,000.00 - ₹35,000.00 per month Benefits: Health insurance Schedule: Day shift Supplemental Pay: Yearly bonus Application Question(s): What is your current CTC & expected CTC? How many years of sheet metal fabrication industry experience you have? What is your Notice period? Experience: total work: 2 years (Required) Location: Bhandup West, Mumbai, Maharashtra (Required) Work Location: In person Application Deadline: 25/06/2025

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors. Siemens EDA is a global technology leader in Electronic Design Automation software. Their software tools empower companies worldwide to develop innovative electronic products efficiently. By using these tools, customers are able to advance technology and physics boundaries to deliver superior products in the complex realm of chip, board, and system design. This is your role. Aprisa provides comprehensive functionality for top-level hierarchical design and block-level implementation for intricate digital IC designs. The detail-route-centric architecture and hierarchical database at Aprisa facilitate the acceleration of design closure and attainment of optimal quality results within a driven runtime. Aprisa is currently engaged in developing the next-generation RTL-to-GDSII solution and is seeking individuals to join this pioneering journey. **Role:** - Drive and oversee the design and development of various aspects of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Guide and lead team members towards successful project completion by introducing innovative and effective solutions. - Collaborate with a dedicated team of experts. **Must-Have Requirements:** - Bachelor's or Master's degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Proficient in C/C++, algorithms, and data structures. - Strong problem-solving and analytical skills. - Leadership abilities to inspire and support the team with your expertise. **Great to Have Experience in:** In this role, you will have the opportunity to work with RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Furthermore, you will be involved in designing C or RTL IPs, optimizing RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly appreciated, along with your proficiency in scripting languages like Python and TCL. Join Siemens, a diverse collective of over 377,000 individuals shaping the future in more than 200 countries. Siemens is committed to equality and encourages applications that reflect the diversity of the communities where they operate. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help shape tomorrow!,

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors who are passionate about electronic design automation software. As a global technology leader, Siemens EDA provides innovative tools that empower companies worldwide to develop cutting-edge electronic products efficiently. By utilizing our software solutions, our customers can navigate the complexities of chip, board, and system design while pushing the boundaries of technology and physics to deliver superior products. Your Role: As part of the Aprisa team, you will play a crucial role in the development of top-level hierarchical design and block-level implementation for complex digital IC designs. Leveraging our detail-route-centric architecture and hierarchical database, you will expedite design closure and achieve optimal quality results within a driven runtime. Join us in shaping the next-generation RTL-to-GDSII solution and become an integral part of this innovative journey! Key Responsibilities: - Drive and oversee the design and development of various components of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Provide guidance and leadership to ensure successful project completion through innovative and effective solutions. - Collaborate with a dedicated team of experts to achieve common goals. Requirements: - Hold a B.Tech or M.Tech degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Possess a strong grasp of C/C++, algorithms, and data structures. - Demonstrate exceptional problem-solving and analytical skills. - Lead and motivate the team with your expertise. Desirable Experience: You will have the opportunity to: - Develop RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. - Design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. - Utilize parallel algorithms and job distribution strategies, along with proficiency in scripting languages like Python and TCL. Join Siemens: Siemens is a global community of over 377,000 individuals working together to shape the future across 200 countries. We value diversity and equality, and we welcome applications that represent the various communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help us pioneer tomorrow!,

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Design For Testability - DFT. Experience: 5-8 Years.

Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Job Description In your new role you will: Drive and manage as technical member of a self contained DFT team which is responsible of: The DFT implementation of latest Infineon microcontroller products Scan insertion , ATPG, LBIST and MBIST Verification of the DFT implementation and Test pattern delivery for production testing Support the Silicon bringup activities to guarantee highest stability of the test pattern Contribute to the overall microcontroller DFT methodology Coordination of DFT workpackage s and hands-on work, status reporting Interfacing with project management, layout team and test engineering Your Profile You are best equipped for this task if you have: At least 6+ years of experience in DFT of highly complex SoCs A university degree in Electrical Engineering, Microelectronics, Physics or a similar field. Profound knowledge about semiconductor products. Expert Knowledge of DFT methods for state-of-the-art MPU/MCU products. Working knowledge of test concept or DFT concept definition. Strong track record of scan insertion and ATPG Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Experience of debugging test pattern issues Programming or scripting experience Very good soft skills and experience in leading Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Job Description In your new role you will: The DFT implementation of latest Infineon microcontroller products Scan insertion, ATPG, LBIST and MBIST Verification of the DFT implementation and Test pattern delivery for production testing Support the Silicon bring up activities to guarantee highest stability of the test pattern Contribute to the overall microcontroller DFT methodology Coordination of DFT work packages and hands-on work, status reporting Interfacing with project management, layout team and test engineering Your Profile You are best equipped for this task if you have: At least 3+ years of experience in DFT of highly complex SoCs A university degree in Electrical Engineering, Microelectronics, Physics or a similar field. Profound knowledge about semiconductor products. Expert Knowledge of DFT method s for state-of-the-art MPU/MCU products. Working knowledge of test concept or DFT concept definition. Strong track record of scan insertion and ATPG Very good knowledge of DFT RTL insertion including MBIST and SRAM repair Experience of debugging test pattern issues Programming or scripting experience Very good soft skills and experience in leading Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

: As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle. Responsibilities: Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus). Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power. Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting. Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization. Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff. Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments. Support signoff reviews, audits, and compliance to power specifications and constraints. Provide mentorship and technical leadership within the team and across global sites. Required Skills and Experience : Proven experience of 5+ years in power estimation, optimization, and methodology development at the gate-level/netlist stage. Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows. Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains. Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows. Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads. Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules. Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions. Nice To Have Skills and Experience : Experience with UPF/CPF power intent validation and integration. Exposure to thermal and IR-drop analysis in relation to power consumption. Familiarity with AI/ML-based power modeling or anomaly detection. Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs. Participation in EDA tool evaluations, benchmarking, and vendor teamwork. Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Hybrid Working at Arm #LI-BB1 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm

: As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments. Responsibilities: Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings). Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP. Ensure power intent consistency and early issue detection through collaboration with design and verification teams. Integrate structural checks into signoff regressions with high coverage and low false positives. Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency. Drive global adoption through documentation, training, and support. Assist in audits, quality reviews, and milestone checks. Required Skills and Experience : 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows. Deep understanding of power intent specs, domain partitioning, isolation, and retention. Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP. Skilled in scripting (Python, Perl, TCL) for flow automation. Experience with large SoC/IP designs across advanced nodes. Confirmed ability to debug structural issues and drive closure. Strong communication and documentation skills. Nice To Have Skills and Experience : Experience with formal verification or functional simulation for power-aware designs. Knowledge of complex power analysis and correlation with structural checks. Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs. Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows. Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications. Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Hybrid Working at Arm #LI-BB1 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm