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Setup ASIC QA flows for RTL design quality checks.
Understand the design: top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.
Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.
Checking the flow errors, design errors & violations and reviewing the reports.
Debugging CDC, RDC issues and come up with the RTL fixes.
Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.
Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.
Flows or Design porting to different technology libraries.
Generating RAMs based on targeted memory compilers and integrating with the RTL.
Running functional verification simulations as needed.
Job Requirements:
ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes.
Modern SOC tools including Spyglass, Synopsys Design Compiler & Primetime, Questa CDC, Cadence Conformal, VCS simulation.
Experience in signoff of front-end quality checks & metrics for various milestones of the project.
TCL, Perl, Python scripting.
B.E/M.E/M.Tech or B.S/M.S in EE/CE with
Proxelera
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hyderābād
Salary: Not disclosed
hyderabad, telangana
Experience: Not specified
Salary: Not disclosed
