Verification Engineer

#Connections #Hiring #VerificationEngineer #Hyderabad #Experience

Hi Connections,

We are hiring....

Job Title: Verification Engineer

Location: Hyderabad / Bangalore / Hybrid

Department: Semiconductor / VLSI Design Verification

Employment Type: Full-Time

Experience: 3+Years

Job Summary

We are seeking a detail-oriented Verification Engineer to ensure functional correctness and robustness of complex SoC/ASIC designs. The role involves creating verification environments, developing testbenches, executing test plans, and debugging issues in collaboration with RTL, architecture, and physical design teams.

Key Responsibilities

● Develop and execute verification plans based on architecture and design specifications.

● Create SystemVerilog/UVM-based testbenches for block-level and top-level verification.

● Implement constrained-random, directed, and coverage-driven verification methodologies.

● Perform functional coverage analysis to ensure thorough testing.

● Debug RTL issues by analyzing simulation waveforms and working with design engineers.

● Integrate third-party IPs and verify their functionality in the system.

● Automate regression runs and maintain test environments.

● Document verification processes, results, and closure reports.

Required Skills & Qualifications

● Bachelor’s/Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or related field.

● 3+ years of experience in ASIC/SoC verification.

● Strong proficiency in SystemVerilog and UVM methodology.

● Experience with simulation tools (Synopsys VCS, Cadence Xcelium, Mentor QuestaSim).

● Understanding of AMBA protocols (AXI, AHB, APB) and other standard interfaces.

● Familiarity with functional coverage, code coverage, and assertion-based verification (SVA).

● Strong debugging skills using waveforms and simulation logs.

Preferred Qualifications

● Experience with low-power verification (UPF/CPF).

● Knowledge of FPGA-based verification and emulation platforms.

● Exposure to AI/ML accelerator verification or DSP systems.

● Familiarity with Python/TCL/Perl scripting for automation.

● Experience with formal verification tools (JasperGold, VC Formal).

Interested guys, kindly share your updated profile to pavani@sandvcapitals.com or reach us on 7995292089.

Thank you.

Job Type: Full-time

Pay: ₹1,200,000.00 - ₹1,500,000.00 per year

Experience:

• ASIC/SoC Verification: 3 years (Required)

Work Location: In person