Verification Engineer

Role & responsibilities

• Add checkers/monitors (limits, windows, settling, ripple, droop/load-line) and sampledvalue

  SVA

  where appropriate.
• Run regressions, triage failures, file bugs with clear waveforms/logs, and assist with root-cause alongside analog/digital design teams.
• Help maintain

  connect rules/IEs

  and config (Hierarchy Editor) so analog to digital boundaries (electrical to wreal/logic) are clean and deterministic.
• Script automation for netlisting, runs, and data reduction (Perl, Python, Ocean).

• Implement testcases from a verification plan for PMIC/VRM blocks (Power up tests, functional test, Power consumption).
• Write plain SV and UVM testcases
• Build SV

  RNM/Verilog-A

  models (e.g. inductor/cap modelling, current-sense modelling etc.) and correlate key behaviours to SPICE at nominal corners.
• Create stimuli: supply ramps, load/line transients, soft-start, mode changes (AVS/SVID/SVI3), fault injections (OCP/OVP/UVP/OTP).

• Understanding of PMIC/VRM concepts: soft-start, CCM/DCM, load-line/droop, protections, telemetry.
• Familiar with Cadence flow:

  Virtuoso/ADE (Explorer/Assembler), Hierarchy Editor/config views, Xcelium/AMS Designer, SimVision

  .
• Scripting in

  Python/Perl

• 2- 5 years

  in AMS verification or mixed-signal design/verification (internships count if handson).
• Working knowledge of

  SystemVerilog + UVM

  , and exposure to

  UVM-MS / Wreal (RNM)

  .
• Basic

  Verilog-A/AMS

  and

  SPICE

  (Spectre/APS/FX) usage; able to run sims and read waveforms.

Preferred candidate profile