Verification Engineer

Role Overview: As a Verification Engineer, you will utilize your 2+ years of experience in ASIC/FPGA verification to develop test plans and verification strategies that thoroughly validate requirements and specifications. Your expertise in developing SV + UVM based verification environment components and creating tests using constrained random based test sequences will be essential for success in this role. Key Responsibilities: - Develop test plans and verification strategies - Develop SV + UVM based verification environment components - Implement functional coverage and resolve coverage gaps - Write tests to ensure comprehensive verification - Contribute to code coverage activities - Enhance the overall verification process Qualifications Required: - Strong problem-solving skills - Familiarity with scripting languages like GNU make, Perl, and Python - Experience in FPGA verification compliance to DO-254 standards - Exposure to verifying DSP blocks using fixed-point operations Additional Details: Your ability to communicate effectively, both verbally and in writing, will be crucial in ensuring successful collaboration and project outcomes. If you are a trained fresher with a passion for verification engineering, you are encouraged to apply and contribute your skills to our dynamic team.,