Verification Engineer

As a Verification Engineer, you will be responsible for utilizing your 2+ years of experience in ASIC/FPGA verification to develop test plans and verification strategies that thoroughly and effectively validate requirements and specifications. Your expertise in developing SV + UVM based verification environment components, such as agents/UVCs, scoreboards, predictors/reference models, and creating tests using constrained random based test sequences will be essential for success in this role. Your role will also involve implementing functional coverage, identifying and resolving coverage gaps, and writing tests to ensure comprehensive verification. Additionally, you will have the opportunity to contribute to code coverage activities and enhance the overall verification process. To excel in this position, you should possess strong problem-solving skills and be capable of working both independently and collaboratively as part of a team. Your familiarity with scripting languages like GNU make, Perl, and Python will be advantageous, along with any experience in FPGA verification compliance to DO-254 standards. Exposure to verifying DSP blocks, such as filters, adders, multipliers, and limiters using fixed-point operations, will further enhance your contributions to the verification process. Overall, your ability to communicate effectively, both verbally and in writing, will be crucial in ensuring successful collaboration and project outcomes. If you are a trained fresher with a passion for verification engineering, you are also encouraged to apply and contribute your skills to our dynamic team.,