1597 Tcl Jobs - Page 29

BENGALURU, KARNATAKA, INDIA FULL-TIME HARDWARE ENGINEERING 3559 Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms. In this hybrid role, you will report to an ASIC Design Manager This position will require the ability to work some hours that align with the team in the Pacific Daylight Time (PDT) zone on an as needed basis. You will: Participate in the Physical Design of advanced silicon for our self-driving cars Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS with a focus on floorplanning and assembly Collaborate with internal logic and internal and external PD teams to achieve the best PPA possible You have: 5+ years of experience on PD design tasks in advanced silicon nodes with a minimum of 2 tapeouts Expertise in generating and maintaining design-rule-check (DRC) clean floorplans (DEF) including pin placement and layer assignment and an understanding of abutted and non-abutted construction methodologies Familiarity with entire RTL-to-GDS flow with hands-on experience with Synthesis, PNR, STA, and timing closure Ability to automate EDA tasks through scripting. Competency with at least one EDA scripting language (TCL, skill, python) Excellent verbal and written communication skills due to need to work with internal and external teams We prefer: Experience with SDC generation, verification, and maintenance Experience working with external partners on PD closure Passion and experience for scripting (beyond driving EDA tools) Understanding of RC fundamentals Deep understanding of performance, power and area (PPA) tradeoffs Familiarity with back end flows (PI/SI, DRC/LVS, etc) May require infrequent travel to Mountain View, CA or to partner sites (Up to 15%) The expected base salary range for this full-time position is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range ₹5,500,000—₹6,650,000 INR

Location Karnataka Bengaluru Experience Range 5 - 10 Years Job Description 3+ years to 10 yrs design experience Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and it’s design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals

Seeking a highly experienced Physical Design Methodology/CAD manager to lead/build a team in Bangalore, India. Key Responsibilities Looking for someone with a blend of technical expertise and strong management skills Experience managing/building a team and ability to manage timelines and multiple on-going projects Expertise in PDK enablement and physical design concepts Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Functional Knowledge Demonstrates comprehensive understanding of concepts and principles within own job family and knowledge of other related job families Business Expertise Applies in-depth understanding of how own discipline integrates within the segment/function Leadership Manages multiple related teams, sets organizational priorities and allocates resources Problem Solving Identifies and resolves complex technical, operational and organizational problems Impact Impacts the business results of a team or area by supporting and funding of projects, products, services and/or technologies and developing policies and plansGuided by business unit, department or sub-functional business plans interpersonal Skills Influences others internally and externally, including senior management.

Job TitleStaff Engineer- Automation Framework LocationBengaluru Work EmploymentFull time DepartmentWireless DomainTesting Reporting toPrincipal Engineer : Tejas Networks is a global broadband, optical and wireless networking company, with a focus on technology, innovation and R&D. We design and manufacture high-performance wireline and wireless networking products for telecommunications service providers, internet service providers, utilities, defence and government entities in over 75 countries. Tejas has an extensive portfolio of leading-edge telecom products for building end-to-end telecom networks based on the latest technologies and global standards with IPR ownership. We are a part of the Tata Group, with Panatone Finvest Ltd. (a subsidiary of Tata Sons Pvt. Ltd.) being the majority shareholder. Tejas has a rich portfolio of patents and has shipped more than 900,000 systems across the globe with an uptime of 99.999%. Our product portfolio encompasses wireless technologies (4G/5G based on 3GPP and O-RAN standards), fiber broadband (GPON/XGS-PON), carrier-grade optical transmission (DWDM/OTN), packet switching and routing (Ethernet, PTN, IP/MPLS) and Direct-to-Mobile and Satellite-IoT communication platforms. Our unified network management suite simplifies network deployments and service implementation across all our products with advanced capabilities for predictive fault detection and resolution. As an R&D-driven company, we recognize that human intelligence is a core asset that drives the organization’s long-term success. Over 60% of our employees are in R&D, we are reshaping telecom networks, one innovation at a time. Why join Tejas: We are on a journey to connect the world with some of the most innovative products and solutions in the wireless and wireline optical networking domains. Would you like to be part of this journey and do something truly meaningfulChallenge yourself by working in Tejas’ fast-paced, autonomous learning environment and see your output and contributions become a part of live products worldwide. At Tejas, you will have the unique opportunity to work with cutting-edge technologies, alongside some of the industry’s brightest minds. From 5G to DWDM/ OTN, Switching and Routing, we work on technologies and solutions that create a connected society. Our solutions power over 500 networks across 75+ countries worldwide, and we’re constantly pushing boundaries to achieve more. If you thrive on taking ownership, have a passion for learning and enjoy challenging the status quo, we want to hear from you! Who we are This team is responsible for Platform and software validation for the entire product portfolio. They will develop automation Framework for the entire product portfolio. Team will develop and deliver customer documentation and training solutions. Compliance with technical certifications such as TL9000 and TSEC is essential for ensuring industry standards and regulatory requirements are met. Team works closely with PLM, HW and SW architects, sales and customer account teams to innovate and develop network deployment strategy for a broad spectrum of networking products and software solutions. As part of this team, you will get an opportunity to validate, demonstrate and influence new technologies to shape future optical, routing, fiber broadband and wireless networks. What you work: You will have complete ownership for preparing test automation solution & designing automation framework Understanding, maintaining and enhancing the multifaceted Frameworks Architect & design tools required for PV qualification Collaborate with product teams and PV teams to strategize & align long term solution for test automation including roadmap, tools, framework & approach. Documentation of the tools and framework features developed. Mandatory skills: BE/B.Tech./M.Tech. (EC/EE/CS) Degree with 10+ yrs. Extensive hands-on experience designing / developing automation frameworks Should be experienced with automation development from PV stand point Hands-on experience with tools development in PHP, JSP, Java, Python, TCL, MySQL and Web technologies is a must Working knowledge of data networking protocols Must be detail oriented and possess excellent communications skills Desired skills: FW development in Telecom using OO based design patterns will be a plus Experience in Selenium and UI open-source framework development is a plus Passion for achieving excellence in process, product quality and reliability Preferred Qualifications Experience: 10 to 14 years’ experience from Telecommunication or Networking background. Education: Tech/BE (CSE/ECE/EEE/IS) or any other equivalent degree Candidate should have knowledge in Automation Framework Testing/Development. Diversity and Inclusion Statement : Tejas Networks is an equal opportunity employer. We celebrate diversity and are committed to creating all-inclusive environment for all employees. We welcome applicants of all backgrounds regardless of race color, religion, gender, sexual orientation, age or veteran status. Our goal is to build a workforce that reflects the diverse communities we serve and to ensure every employee feels valued and respected.

Job TitleSenior Engineer- Automation Framework LocationBengaluru Work EmploymentFull time DepartmentWireless DomainTesting Reporting toLead Engineer : Tejas Networks is a global broadband, optical and wireless networking company, with a focus on technology, innovation and R&D. We design and manufacture high-performance wireline and wireless networking products for telecommunications service providers, internet service providers, utilities, defence and government entities in over 75 countries. Tejas has an extensive portfolio of leading-edge telecom products for building end-to-end telecom networks based on the latest technologies and global standards with IPR ownership. We are a part of the Tata Group, with Panatone Finvest Ltd. (a subsidiary of Tata Sons Pvt. Ltd.) being the majority shareholder. Tejas has a rich portfolio of patents and has shipped more than 900,000 systems across the globe with an uptime of 99.999%. Our product portfolio encompasses wireless technologies (4G/5G based on 3GPP and O-RAN standards), fiber broadband (GPON/XGS-PON), carrier-grade optical transmission (DWDM/OTN), packet switching and routing (Ethernet, PTN, IP/MPLS) and Direct-to-Mobile and Satellite-IoT communication platforms. Our unified network management suite simplifies network deployments and service implementation across all our products with advanced capabilities for predictive fault detection and resolution. As an R&D-driven company, we recognize that human intelligence is a core asset that drives the organization’s long-term success. Over 60% of our employees are in R&D, we are reshaping telecom networks, one innovation at a time. Why join Tejas: We are on a journey to connect the world with some of the most innovative products and solutions in the wireless and wireline optical networking domains. Would you like to be part of this journey and do something truly meaningfulChallenge yourself by working in Tejas’ fast-paced, autonomous learning environment and see your output and contributions become a part of live products worldwide. At Tejas, you will have the unique opportunity to work with cutting-edge technologies, alongside some of the industry’s brightest minds. From 5G to DWDM/ OTN, Switching and Routing, we work on technologies and solutions that create a connected society. Our solutions power over 500 networks across 75+ countries worldwide, and we’re constantly pushing boundaries to achieve more. If you thrive on taking ownership, have a passion for learning and enjoy challenging the status quo, we want to hear from you! Who we are This team is responsible for Platform and software validation for the entire product portfolio. They will develop automation Framework for the entire product portfolio. Team will develop and deliver customer documentation and training solutions. Compliance with technical certifications such as TL9000 and TSEC is essential for ensuring industry standards and regulatory requirements are met. Team works closely with PLM, HW and SW architects, sales and customer account teams to innovate and develop network deployment strategy for a broad spectrum of networking products and software solutions. As part of this team, you will get an opportunity to validate, demonstrate and influence new technologies to shape future optical, routing, fiber broadband and wireless networks. What you work: You will have complete ownership for preparing test automation solution & designing automation framework Understanding, maintaining and enhancing the multifaceted Frameworks Architect & design tools required for PV qualification Collaborate with product teams and PV teams to strategize & align long term solution for test automation including roadmap, tools, framework & approach. Documentation of the tools and framework features developed. Mandatory skills: BE/B.Tech./M.Tech. (EC/EE/CS) Degree with 3+ yrs. Extensive hands-on experience designing / developing automation frameworks Should be experienced with automation development from PV stand point Hands-on experience with tools development in PHP, JSP, Java, Python, TCL, MySQL and Web technologies is a must Working knowledge of data networking protocols Must be detail oriented and possess excellent communications skills Desired skills: FW development in Telecom using OO based design patterns will be a plus Experience in Selenium and UI open-source framework development is a plus Passion for achieving excellence in process, product quality and reliability Preferred Qualifications Experience: 3 to 6 years’ experience from Telecommunication or Networking background. Education: Tech/BE (CSE/ECE/EEE/IS) or any other equivalent degree Candidate should have knowledge in Automation Framework Testing/Development. Diversity and Inclusion Statement : Tejas Networks is an equal opportunity employer. We celebrate diversity and are committed to creating all-inclusive environment for all employees. We welcome applicants of all backgrounds regardless of race color, religion, gender, sexual orientation, age or veteran status. Our goal is to build a workforce that reflects the diverse communities we serve and to ensure every employee feels valued and respected.

Job TitleLead Engineer- Automation Framework LocationBengaluru Work EmploymentFull time DepartmentWireless DomainTesting Reporting toStaff Engineer : Tejas Networks is a global broadband, optical and wireless networking company, with a focus on technology, innovation and R&D. We design and manufacture high-performance wireline and wireless networking products for telecommunications service providers, internet service providers, utilities, defence and government entities in over 75 countries. Tejas has an extensive portfolio of leading-edge telecom products for building end-to-end telecom networks based on the latest technologies and global standards with IPR ownership. We are a part of the Tata Group, with Panatone Finvest Ltd. (a subsidiary of Tata Sons Pvt. Ltd.) being the majority shareholder. Tejas has a rich portfolio of patents and has shipped more than 900,000 systems across the globe with an uptime of 99.999%. Our product portfolio encompasses wireless technologies (4G/5G based on 3GPP and O-RAN standards), fiber broadband (GPON/XGS-PON), carrier-grade optical transmission (DWDM/OTN), packet switching and routing (Ethernet, PTN, IP/MPLS) and Direct-to-Mobile and Satellite-IoT communication platforms. Our unified network management suite simplifies network deployments and service implementation across all our products with advanced capabilities for predictive fault detection and resolution. As an R&D-driven company, we recognize that human intelligence is a core asset that drives the organization’s long-term success. Over 60% of our employees are in R&D, we are reshaping telecom networks, one innovation at a time. Why join Tejas: We are on a journey to connect the world with some of the most innovative products and solutions in the wireless and wireline optical networking domains. Would you like to be part of this journey and do something truly meaningfulChallenge yourself by working in Tejas’ fast-paced, autonomous learning environment and see your output and contributions become a part of live products worldwide. At Tejas, you will have the unique opportunity to work with cutting-edge technologies, alongside some of the industry’s brightest minds. From 5G to DWDM/ OTN, Switching and Routing, we work on technologies and solutions that create a connected society. Our solutions power over 500 networks across 75+ countries worldwide, and we’re constantly pushing boundaries to achieve more. If you thrive on taking ownership, have a passion for learning and enjoy challenging the status quo, we want to hear from you! Who we are This team is responsible for Platform and software validation for the entire product portfolio. They will develop automation Framework for the entire product portfolio. Team will develop and deliver customer documentation and training solutions. Compliance with technical certifications such as TL9000 and TSEC is essential for ensuring industry standards and regulatory requirements are met. Team works closely with PLM, HW and SW architects, sales and customer account teams to innovate and develop network deployment strategy for a broad spectrum of networking products and software solutions. As part of this team, you will get an opportunity to validate, demonstrate and influence new technologies to shape future optical, routing, fiber broadband and wireless networks. What you work: You will have complete ownership for preparing test automation solution & designing automation framework Understanding, maintaining and enhancing the multifaceted Frameworks Architect & design tools required for PV qualification Collaborate with product teams and PV teams to strategize & align long term solution for test automation including roadmap, tools, framework & approach. Documentation of the tools and framework features developed. Mandatory skills: BE/B.Tech./M.Tech. (EC/EE/CS) Degree with 6+ yrs. Extensive hands-on experience designing / developing automation frameworks Should be experienced with automation development from PV stand point Hands-on experience with tools development in PHP, JSP, Java, Python, TCL, MySQL and Web technologies is a must Working knowledge of data networking protocols Must be detail oriented and possess excellent communications skills Desired skills: FW development in Telecom using OO based design patterns will be a plus Experience in Selenium and UI open-source framework development is a plus Passion for achieving excellence in process, product quality and reliability Preferred Qualifications Experience: 6 to 10 years’ experience from Telecommunication or Networking background. Education: Tech/BE (CSE/ECE/EEE/IS) or any other equivalent degree Candidate should have knowledge in Automation Framework Testing/Development. Diversity and Inclusion Statement : Tejas Networks is an equal opportunity employer. We celebrate diversity and are committed to creating all-inclusive environment for all employees. We welcome applicants of all backgrounds regardless of race color, religion, gender, sexual orientation, age or veteran status. Our goal is to build a workforce that reflects the diverse communities we serve and to ensure every employee feels valued and respected.

As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level Work with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development Senior engineers are also encouraged to support junior members Required Skills and Experience 8+ years of proven experience in working on IP/Subsystem/Soc Verification Experienced in Protocol on Flash Storage device Controller with unipro and MIPI PHY Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, Low Power/ Power Management Good Skills in System Verilog, shell programming/scripting (e g Tcl, Perl, Python etc ) Experienced in one or more of various verification methodologies UVM, formal and low power Exposure to all stages of verification requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support Experience with various front-end verification tools Dynamic simulation tools, Static Simulation tools and Debuggers Nice To Have Skills and Experience Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture / micro-architectures! Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran Hybrid Working at Arm Arms hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you In Return We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together These behaviors are assessed as part of the hiring process Partner and customer focus Collaboration and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises We offer a hybrid approach to home and office working to provide an adaptable experience for all employees We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm com To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process

Job Overview Arms Design For Test methodology team works on DFT for projects, including soft IP, hard macros, SOCs and physical library IP across all the Arm design sites In addition, this team builds and drives DFT methodology and flows throughout all of Arm and works to get support from EDA vendors to support our methodologies Responsibilities Support DFT on multiple types of projects in multiple design centers and apply innovative DFT techniques and affect the content of forthcoming CPU, GPU, ML and systems IP, some years before they appear in mainstream products This candidate will supply to DFT methodology by crafting flows, evaluating tool capabilities, helping other specialists on projects, detailing work through documentation, working with EDA vendors and propagating DFT methodologies This position may also include meeting with customers for DFT training or to address DFT concerns Required Skills And Experience Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills is considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree or equivalent experience (in Electronic Engineering, Computer Engineering, or other relevant technical subject area) ?Nice To Have? Skills And Experience Familiarity with IEEE standards Familiarity with supporting silicon into volume production Knowledge of SSN and 3DIC Gained some exposure to digital ASIC frontend and backend design & verification processes Familiarity with SOC architectures (Auto/Infrastructure/Client) and low power design practices would be an advantage In Return You will have the opportunity to craft the future of Design-for-Test at Arm, working on industry-leading IP that powers next-generation CPUs, GPUs, and AI systems Youll be part of a collaborative team driving DFT methodologies across global design centers, with access to ground breaking tools, training, and support from leading EDA partners Arm offers a flexible hybrid work model and a competitive benefits package?including private medical insurance, generous pension contributions, sabbaticals, wellness initiatives, and continuous professional development?to support your success and growth in this high-impact role Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm com To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

We’re looking for a highly analytical, creative, and passionate brand manager who can work across geographies to be a part of the brand team. Designated as Deputy General Manager – Brand Marketing (Global Marketing) Located in India Reports to Chief of Brand What You’ll Do: Be the Brand Champion: Define & Evolve : Take charge of developing and refining our brand's voice and positioning. Ensure it resonates with our stakeholders across customers, analysts, shareholders. Building, managing, and externally positioning brand communications strategies in partnership with the overall TCL Communications team and brand marketing function. Drive thought leadership and content development to advance brand narrative and awareness among key audiences and across geographies. Ensure brand's image, messaging, and positioning are consistent and effectively communicated across social media platforms. Oversee social media strategy, content creation, engagement, and analysis to build and maintain a strong brand presence online. Campaign Build : Lead the creation of compelling and innovative marketing campaigns that elevate our brand across all touchpoints—whether it’s digital, print, or experiential marketing. Customer Insights : Dive deep into consumer behaviour and market trends to guide and shape marketing strategies. Your understanding of the customer will drive everything we do. Drive Growth & Performance: Impactful Strategy : Develop customer insight drives campaigns to build a compelling and relevant campaign ROI Focused : Manage the marketing budget effectively, ensuring that every campaign maximizes ROI while staying true to brand values. Brand track Survey: Gather data through various track surveys to monitor brand health, track brand awareness, and make informed decisions about brand strategy & marketing campaigns.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role AMD is looking for a senior software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The Person The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for Software engineering development, and is diligent and passionate about Technology. A successful candidate will need to employ strong knowledge in computer technologies, leadership skills in technical areas, and SW engineering expertise as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators. Key Responsibilities Develop and drive execution of comprehensive, highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team Collaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results Preferred Experience Strong digital design and simulations basics RTL (VHDL, Verilog & System Verilog) coding skills Understanding of FPGA design flow and tools (Synthesis, Simulation and implementation) ASIC/FPGA verification experience - VHDL and Verilog Xilinx Vivado Design Suite experience Hands on experience on simulators like XSIM, Questa, Modelsim, VCS etc. Advanced Debug skills in software environment or strong problem-solving skills Hands on experience with scripting preferably tcl, pearl and python Academic Credentials Bachelor’s or Master’s degree in Computer/Software Engineering, Computer Science, or related technical discipline Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 5 years of experience in characterizing standard-cells or memory. 5 years of experience in static timing analysis and simulation. Preferred qualifications: Master's degree in VLSI Integration, Computer Engineering, Electronics Engineering, or a related field. Experience in spice and statistical circuit simulators, including FineSim, HSpice, Spectre, and Solido. Experience in Practical Extraction and Report Language (PERL)/Shell/Transaction Control Language (TCL) scripting or similar languages. Understanding of Complementary Metal-Oxide-Semiconductor (CMOS) circuits and timing concepts (e.g., setup, hold). Ability to automate repeatable tasks to improve efficiency/productivity using the scripting languages. Proficiency with industry-standard Electronic Design Automation (EDA) tools for implementation and signoff. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google Silicon team develops custom silicon solutions that provide differentiated user experiences in Google hardware products and optimize performance and power for the use cases. This includes SoCs and other mixed signal, logic, and sensor integrated circuits for our product portfolio. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work with Post-Si teams to improve and debug Vmin and yield related issues. Explore and specify new custom circuit opportunities for optimized Power Performance Area (PPA) for high-performance, low-power subsystems. Work with the testchip teams on latest process nodes to build, validate and characterize custom IPs. Build automation for circuit design simulation and analysis. Work with cross-functional teams on circuit design, physical design and sign-off methodology teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Understand RTL at structural level, IP boundaries, IP parameters. Understand IP design. Add assertions where needed. Generate various constraints necessary for the IP. RTL build flow setup and maintenance. Do the quality checks of the IP like Lint/CDC/RDC/Synth/Timing checks/waiver creation across milestones. Participate in IP integration to the subsystem level. Write sample test bench to verify the basic functionality of the IP/block. Do the first level of triage of the functional issues reported. Understand the reports out of quality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fix in the RTL Work with functional verification team to meet coverage and quality standards. Guarantee quality/timely deliverables meeting project’s schedule. Help to improve/automate design process. PREFERRED EXPERIENCE: Knowledge of ASIC development flows Knowledge of front-end RTL design tools and methodologies. Knowledge of system Verilog Multi-clock domain designs. Design constraints for synthesis and static timing analysis. Experience in RTL linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power) Knowledge of AXI/AMBA protocol Ability to create a simple SV based Test benches, create sanity test plan, run the test cases Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power. Verification - coverage, test plan, debug Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal) Ability to work and effectively collaborate with partners Knowledge of scripting languages like Perl, tcl or cshell Experience with DMAs, PCIe, ordering, data path virtualization, performance, flow control a plus. TekWissen® Group is an equal opportunity employer supporting workforce diversity.

Associate / Lead, Enovia CAD Integration Location: Chennai, Tamil Nadu, India Shift: 2 PM – 11 PM IST (Swing Shift) Work Mode: Hybrid (2–3 days/week in-office) Experience: 3–5 Years Education: Bachelor’s / Master’s / Doctorate in Engineering or related field Role Summary Seeking an experienced Enovia 3DExperience professional to lead CAD integration and functional configuration projects. You’ll work closely with architects, PMs, and business teams to translate business needs into scalable PLM solutions. Key Responsibilities Participate in design workshops and provide technical inputs Translate business requirements into IT specifications Develop and execute integration test cases Work with Enovia PLM integrations including CAD & SAP Support BOM & Change Management modules Develop and review technical designs and JPOs Configure 3DExperience apps like Product Structure, 3D Visualization, 3DPlay Must-Have Skills 3–5 years in Enovia 3DExperience solution development Expertise in CAD integrations: Creo, SolidWorks, Inventor, Solid Edge Knowledge of XPDM, PowerBy architecture Familiar with UPS data model and visualization tools Proficiency in Enovia development: JPOs, JSPs, TCL, MQL Experience with Oracle SQL, web services-based integrations

Looking for a high-performance individual to work on the Synopsys next generation emulation solutions encompassing Virtual and Physical interface solutions on for PCIE, CXL, USB, Ethernet. The selected candidate will work on product verification and product engineering of these products ensuring all system level scenarios in the concerned product/solution are exhaustively verified and gets deployed at hyperscale customers. The person is required to be motivated and self-driven and would work among a knowledgeable and experienced set of people, adding to his/her learning. Academic Qualification/Skills required: B.E / M.E. in Electronic & Communication / Computer Science Engineering High performance individual to work on Synopsys next generation emulation solutions for PCIe, USB, Ethernet protocols Good knowledge of one of peripheral protocols primarily PCIe, USB, Ethernet Knowledge of System Level verification and validation, and digital design concepts Knowledge of languages such as Verilog, System Verilog, C/C++, and scripting languages- Perl/TCL/Shell, Python Knowledge of emulation and prototyping domains an added advantage 6-8 Years of experience in protocols/design verification and validation, scripting, and automation Good communication skills and team player

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job responsibilities: BE/BTECH/ME/MTECH Or Equivalent Degree Very good knowledge on SCAN/ATPG/JTAG/MBIST Experience with one or more chip tape out that includes chip ATE bring up. Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG) Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques. Experience in scan insertion techniques at block level and chip top level. Experience on Memory BIST generation, insertion, verification on RTL/Netlist level. Good knowledge and understanding in Analog PHY and Analog Macro tests. Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards. Good knowledge on test mode timing constraints Good knowledge about running block level and chip STA flows. Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team. Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools) Experience with post-silicon bring up and debug on ATE. Good knowledge on Perl/Tcl scription skills Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization. High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project. Should have B-Tech/M-tech with 5 Years to 15 Years relevant experience. We’re doing work that matters. Help us solve what others can’t.

Work Location:Pan India Experience : 2-15yrs Job Description: Required Skills: Experience in Configuration, Customization , Develop use cases, Testing of Enovia 3D Experience platform. Knowledge of Enovia centrals Widget development. Work Instruction Client Side Development (CAA/EKL/Knowledgeware/Business Logic/Batch) Server Side Development (Java, Webservices, Json, JPO, Security) Widget customization (For later sprints) Experience on Java, J2EE, JSP, CAA, EKL Please share your updated profile to suganya@spstaffing.in if interested.

Meet the Team Internet became a reality because of Cisco and its intelligent innovations in WAN engineering over multiple decades. We are reinventing WAN now and disrupting the market. If you love the challenge of building a highly scalable intelligent distributed system, then please join the party. We are abstracting WAN infrastructure and programmatically building a highly flexible controller-based software defined solution to provide intent based networking. Our solutions provide secure connectivity to user & device from anywhere in the world to their favorite application running in cloud, on premise or as SaaS. We give the opportunity to learn and innovate in a vast technology space of Routing, Security, Analytics, Telemetry, Distributed System, Machine learning and endless other areas. We strive to create an open and transparent culture where we embrace new ideas with open arms. Hardware Routing Platform Software under Catalyst Engineering Routing team builds industry leading Headend SDWAN and Edge routing platforms (Catalyst 8500 and ASR1000) is part of a bigger team that is currently working on building next generation routing and services in controller-based network deployment at scale, enabling the customers to avail secure, reliable, and fast connectivity in a highly distributed SDWAN fabric spanning across the globe connecting thousands of devices and millions of users. Join us and be part of the high energy team, help transform and build intelligent internet. Your Impact You will have the opportunity to work with leading-edge networking technologies in the areas of SDWAN and edge routing platforms and be part of the team responsible for defining, developing, and innovating new and evolving features and architectures in SDWAN and routing. You will work in collaboration with team who will define the next generation ASIC for routing products which would require new architecture for packet forwarding. You will participate in many creative projects, with the authority and scope to apply your expertise in a dynamic engineering environment. Our team values collaboration, learning, paramount focus on quality and customer impact. You will get a chance to work with various teams across varied technologies and will learn and be part of an ever growing, evolving technology. You will be responsible for crafting, coding and testing forwarding components with focus on end-to-end visibility and knowledge. You will have the opportunity to influence the network behavior by collaborating with other Engineers, Technical Leaders and Distinguished engineers across multiple cross-functional teams in Cisco. This role is for you if you believe you are passionate about problem solving, can articulate problems in a way that people start seeing solutions in it as well. You are someone who challenges the status quo and a driver of change. Minimum Qualifications and Requirement: 3-4 years of Industry experience. Hands on experience on End-to-End Software development in a networking company in areas of Platforms, Hardware, bring up, system software, drivers (kernel and user space), bootloaders, BIOS and performance engineering/tuning Strong C programming in Linux and device drivers with skills and familiarity with large software development projects in an UNIX or IOS environment including experience with source code control systems, i.e. ability to search, navigate and handle extremely large code base. Experience with LAN/WAN communication interfaces, Ethernet layer 2, layer 3 technologies. Experience with hardware and software debuggers, GDB, Arium, BDI. Experience with scripting and automation and to be able to design, create and run scripts for longevity tests for platform, e.g Shell, Python, Perl, TCL, Expect. The successful candidate will participate on project teams defining and developing innovative new products based on Cisco technology. Key functions are following: Develop, enhance, verify and sustain embedded system software for complex internetworking products as a key member of a cross-functional team. Perform design trade-off analysis, write software specifications, code, integrate and test new software and hardware, complete product release, and provide field support. Interface with Business Development, External Partners, Hardware Engineering, QA Test and Release Operations throughout the development cycle. Act as Key Decision maker on Technical and Engineering Design issues. Desirable skills: Knowledge or demonstrated experience with high-speed interfaces, PHY, MAC, MACSEC experience will be a plus. Some of the key areas of expertise in addition to Networking domain is platform/System Areas such as kernel bring up, kernel driver development, platform bring up/ management software and Cloud Networking Technologies. Experience in debugging platform issue with i2c, i2c trace analyzers, PCIe. Knowledge of X86, ARM assembly code. Motivated self-starter with good communication and organizational skills, with demonstrated ability to develop and deliver superior products in a cross-functional team environment under aggressive schedules. Knowledge and experience of micro code and forwarding, datapath plus. Knowledge and experience of DPDK is plus. #WeAreCisco (This is the Standard and cannot be changed) #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco’s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco’s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Overview: Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities: Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip’s for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications: Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.