Physical Design Engineer

Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.

In this hybrid role, you will report to an ASIC Design Manager

This position will require the ability to work some hours that align with the team in the Pacific Daylight Time (PDT) zone on an as needed basis.

You will:

• Participate in the Physical Design of advanced silicon for our self-driving cars
• Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS with a focus on floorplanning and assembly
• Collaborate with internal logic and internal and external PD teams to achieve the best PPA possible

You have:

• 5+ years of experience on PD design tasks in advanced silicon nodes with a minimum of 2 tapeouts
• Expertise in generating and maintaining design-rule-check (DRC) clean floorplans (DEF) including pin placement and layer assignment and an understanding of abutted and non-abutted construction methodologies
• Familiarity with entire RTL-to-GDS flow with hands-on experience with Synthesis, PNR, STA, and timing closure
• Ability to automate EDA tasks through scripting. Competency with at least one EDA scripting language (TCL, skill, python)
• Excellent verbal and written communication skills due to need to work with internal and external teams

We prefer:

• Experience with SDC generation, verification, and maintenance
• Experience working with external partners on PD closure
• Passion and experience for scripting (beyond driving EDA tools)
• Understanding of RC fundamentals
• Deep understanding of performance, power and area (PPA) tradeoffs
• Familiarity with back end flows (PI/SI, DRC/LVS, etc)

May require infrequent travel to Mountain View, CA or to partner sites (Up to 15%)