Job Title: Physical Design Engineer
Company: Wipro
Domain: Semiconductor | VLSI | Chip Design
Experience: 7 to 15 Years
Location: Bangalore / Hyderabad / Cochin / Pune
Budget: ₹30 LPA to ₹75 LPA
Work Mode: 5 Days Office

Key Responsibilities:

End-to-end ownership of chip-level and block-level floor planning.
Drive partitioning, placement, clock tree synthesis (CTS), and routing.
Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation.
Perform timing analysis, DRC/LVS closure, and physical verification.
Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams.

Key Skills Required:

Strong experience in chip-level and block-level physical design.
Hands-on expertise with Innovus and/or Fusion Compiler.
Solid understanding of timing, power, signal integrity, and physical verification.
Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus.
Excellent problem-solving and debugging skills.

Interview Process:

L1 Technical Round – Virtual
L2 Final Round – Virtual

Job Types: Full-time, Permanent

Pay: ₹3,000,000.00 - ₹7,500,000.00 per year

Schedule:

Monday to Friday

Ability to commute/relocate:

Pune, Maharashtra: Reliably commute or planning to relocate before starting work (Preferred)

Application Question(s):

End-to-end ownership of chip-level and block-level floor planning?
Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation?
Perform timing analysis, DRC/LVS closure, and physical verification?

Work Location: In person

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