Physical Design Engineer

Key Responsibilities:

• Floor planning:

  Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability.

• Place & Route (P&R):

  Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area).

• Static Timing Analysis (STA):

  Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization.

• Power Analysis & Optimization:

  Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization.

• Signal Integrity & Noise Analysis:

  Perform signal integrity analysis to avoid noise and crosstalk in the design.

• Design Rule Check (DRC) and Layout vs. Schematic (LVS):

  Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic.

• RC Extraction:

  Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies.

• Verification:

  Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met.

• Collaboration:

  Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues.

• Documentation:

  Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference.

Qualifications:

• Education:

  Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree.

• Experience:

• Minimum 3-14 years of experience in ASIC physical design.
• Proficiency in

  place and route

  (P&R),

  static timing analysis

  (STA),

  power analysis

  , and

  DRC/LVS

  checks.
• Experience with tools like

  Cadence Innovus

  ,

  Synopsys IC Compiler

  , or

  Mentor Graphics

  for physical design.
• Knowledge of

  advanced process nodes

  (e.g., 7nm, 5nm) is a plus.

• Technical Skills:

• Proficiency in

  digital design

  concepts and semiconductor process flows.
• Strong knowledge of

  timing optimization

  techniques and

  power optimization

  strategies.
• Familiarity with

  parasitic extraction

  and

  signal integrity

  analysis.
• Ability to script in languages like

  Tcl

  ,

  Python

  , or

  Perl

  to automate tasks.

Preferred Skills:

• Experience with

  3D IC design

  or

  FinFET

  technologies.
• Familiarity with full-chip

  tape-out

  procedures.
• Exposure to

  machine learning

  techniques in physical design optimization will be added advantage.