Posted:7 hours ago|
Platform:
Work from Office
Full Time
We are hiring a skilled Physical Design Engineer with hands-on experience in Cadence Innovus and deep understanding of PnR implementation flows. The role involves complete RTL-to-GDS execution, timing closure, and signoff activities at block and/or top level.
End-to-end physical design implementation using Cadence Innovus
Floorplanning, power planning, placement, CTS, routing, and optimization
Timing convergence across multi-corner/multi-mode
Work with RTL/STA/DFT teams to resolve congestion, noise, IR/EM issues
Run DRC/LVS/STA and signoff checks for tape-out
Cadence Innovus hands-on experience
Physical design flows (PnR)
STA & timing closure
Scripting: Tcl/Shell/Python
7nm/10nm node experience
Low-power design methodologies (UPF/CPF)
Experience in PrimeTime/Calibre/Voltus
Exiger Technologies
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