Physical Design Engineer

As a Senior Physical Design Engineer with 6 years of experience, you will lead the physical implementation of advanced semiconductor projects. Your role will be crucial in shaping the silicon realization of cutting-edge designs, ensuring successful integration from RTL to tape-out. **Key Responsibilities:** - Provide technical guidance and mentoring to physical design engineers. - Interface with front-end ASIC teams to resolve issues. - Implement low-power design techniques such as Voltage Islands, Power Gating, and Substrate-bias. - Work on timing closure for DDR2/DDR3/PCIE interfaces. - Utilize a strong background in ASIC Physical Design including floor planning, P&R, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Use extensive experience and detailed knowledge in Cadence, Synopsys, or Magma physical Design Tools. - Demonstrate expertise in scripting languages like PERL, TCL. - Apply strong Physical Verification skill set. - Conduct Static Timing Analysis in Primetime or Primetime-SI. - Communicate effectively with written and oral skills, documenting plans clearly. - Collaborate with different teams and prioritize work based on project needs. **Qualifications Required:** - Ability to perform top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks. - Experience with 65nm or lower node designs and advanced low power techniques. - Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification. - Bachelors or Masters degree in electronics engineering or related field. This job also requires familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, Mentor Calibre, and knowledge of low-power design techniques and implementation.,