Design Verification Engineer

Softnautics is seeking a skilled Verification Engineer to join our VLSI group function. As a Verification Engineer at Softnautics, you will play a crucial role in the architecture development, implementation, and documentation of verification IPs. You will be responsible for various tasks including SV/VUM coding, test-plan development, assertion and functional coverage coding, simulations, and more. Additionally, you will have the opportunity to lead a small team and contribute to the overall success of our projects. Responsibilities: - Understanding the standards and specifications relevant to the project - Developing and documenting architecture details - Hands-on involvement in all aspects of the verification cycle - Ensuring compliance with the latest methodologies - Creating Verification IPs - Defining Functional Coverage matrix and Comprehensive Test plan - Managing regression and achieving functional coverage closure - Integrating and verifying Design Under Test (DUT) for IP delivery sign-off - Leading a small team of engineers Required Skills: - Hands-on experience in complete verification cycle with a strong understanding of verification concepts - Proficiency in Verilog, SystemVerilog, and UVM - Experience in UVM based Verification IP development - Familiarity with AMBA AXI/AHB/APB System buses - Hands-on experience with protocols such as PCIe, Ethernet, USB, DDR, etc. - Knowledge of System Verilog Assertions - Proficiency in scripting for automation, release processes, simulations, and regressions - Excellent written and oral communication skills Desired Skills: - Experience in leading Verification IP development with junior engineers - Exposure to the full verification cycle If you are a confident, self-motivated individual with strong fundamentals in verification engineering, we encourage you to apply for this exciting opportunity at Softnautics. Join our team and be a part of a collaborative environment focused on delivering high-quality results.,