Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm Hexagon DSP IP's 8+ years of experience in Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075443

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus. o Hands on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs. o Expertise in formal verification with Cadence LEC/ Synopsys Formality o Expertise in writing and debugging timing constraints o Perl and/or TCL scripting, makefile flows. Qualcomm's compute sub system engineers will work on next generation low power, machine Learning sub-system for our system-on-chip (SoC) products used in Smartphone, Automotive and other low power devices. Become a key member of the core team developing fastest smartphone SoC devices implemented on the latest cutting-edge process technologies. In this role candidate will be responsible for compute sub system implementation that includes Physically aware Synthesis -DCG/Fusion Compiler/Genus. In addition, he/she will perform tasks toward constraints development, clock definitions, timing analysis, UPF, CLP check, Formal Verification and ECO flow. He/She will be working closely with physical Design team to optimize designs for power, area, and performance. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075459

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ASIC Frontend Implementation, CDC/RDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC. Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC. Perform RTL Lint and work with the Designers to create waivers. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,). Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 8+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing. Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 5+ years of experience in static verification tools Experience with communicating across functional internal teams and vendors. Experience with Lint, Clock Domain & Reset Domain crossing Experience with SOC CDC signoff Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Experience with communicating across functional internal teams and vendors. Preferred Qualifications: Experience with SOC Design Integration and Front-End Implementation Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make Experience with SOC Design Integration and Front-End Implementation. Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Exp: 12 to 16 years B.E./B.Tech or M.E./M.Tech in Electronics semiconductor/VLSI services with at least 3–5 years in delivery or practice leadership roles. Experience in System Verilog, UVM, test case, coverage, regression.

As a SoC validation enigneer you will play a critical role in ensuring our custom silicon products meet AMD s quality standards and achieve production quality, working hands on you will be responsible for enabling the pre-silicon and post-silicon validation verification of next generation SoCs on multiple platforms. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development teams. THE PERSON: You have a passion and proven track record of emulation domain. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Technical role requirements - 8+ years of experience in Pre & post silicon IP or SOC Validation Working knowledge of the HSIO protocols PCIE, ethernet , ORAN/eCPRI and legacy IO - I2C/I3C, UART, GPIO, SPI Extensive experience with engineering lab equipment, oscilloscopes, protocol analyzers, signal generators, etc. Hand on experience with one or more types of emulators (Palladium, Protium, Zebu ) Hands-on experience and well versed in one or more of the scripting languages like C, tcl and Python. Extensive experience with debug techniques and methodologies. ARM Coresight knowledge is a plus. Ability to develop and execute test cases in both pre and post Si environments In-depth knowledge of PC architectures and system technologies. Attention to detail and the ability to analyze data quickly is a must. Ability to flex responsibilities over the development lifecycle. Knowledge on the system drivers, firmware and software is a plus. Solid grasp of concepts of HW/SW interface Firsthand experience with silicon bringup, complex system debug, or bare-metal programming. Strong programming skills (assembly, C, Perl/Python) Key job responsibilities As an SoC Validation Engineer, you will be responsible for enabling the pre-silicon and post-silicon validation verification of next generation SoCs on multiple platforms such as emulation, prototyping and early silicon. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development teams. Basic Qualifications Bachelor s degree or higher in EE, CE, or CS Very strong problem solving, debug and analysis, and automation skills Experience with verification and validation of complex SOCs Preferred Qualifications Experience in a full development cycle from pre-silicon to silicon bringup MS or PhD in Computer Science, Electrical Engineering or related field Experience with SOC fabrics, memory controllers, and SOC peripherals Excellence in technical communication with peers and non-technical cohorts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /master"™s degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 12+ years Hardware Engineering experience or related work experience. 12+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

At F5, we strive to bring a better digital world to life. Our teams empower organizations across the globe to create, secure, and run applications that enhance how we experience our evolving digital world. We are passionate about cybersecurity, from protecting consumers from fraud to enabling companies to focus on innovation. Everything we do centers around people. That means we obsess over how to make the lives of our customers, and their customers, better. And it means we prioritize a diverse F5 community where each individual can thrive. Role Overview: The Network Support Engineer II (NSE II) is an experienced technical support professional who provides remote assistance on F5 solutions to customers and partners. They manage multiple complex cases, analyze network environments, and apply sound judgment within defined procedures to resolve issues and ensure customer satisfaction. NSE IIs work independently, follow scheduled shifts, and use various troubleshooting tools. They maintain strong relationships with internal teams and external clients, communicate effectively, and take full ownership of cases until resolution. This role will be based in Hyderabad . Sounds interesting? Read on! What you will do: Demonstrates good judgement to select the best methods and techniques to provide a diverse scope of technical support (Level 1 to Level 3) to troubleshoot and resolve hardware and software issues on F5 product and services, based on data analysis of a complex set of customer specific factors. Proactively and effectively communicates status, plan-of-action, and resolution of issues based on an ISO Quality Management System defined set of procedures. Provides F5 customers and partners with a consistently high-quality support experience Participates in on-going training with F5 products and related technologies Maintains high schedule adherence (work hours and on-phone time) Effectively manages case escalations to tier 3 (Engineering Services) while maintaining customer communication, with limited assistance/mentoring from senior support personnel or management Manages multiple routine cases and prioritizes based upon customer and business needs Performs additional projects as required Responsible for upholding F5’s Business Code of Ethics and promptly reporting violations of the code or other company policies. What you will bring: 5 years experience in a professional technical support role or equivalent experience, working with relevant technologies Bachelors BA/BS, Honors, Graduate Certificate preferred. Certification to 201 level certification is expected to be achieved at NSE II level in their core module area of expertise. Level 301 certification is preferred but not expected. Excellent customer service skills together with experience supporting corporate customers and service providers in production environments. Key areas of knowledge – Protocols, Linux, Networking, Popular Public Cloud Vendors, containerization, Experience with AI technology. Thorough understanding and experience with HTTP and web applications and Hands-on technical experience preferred with inter-networking/data center operations. NetworkOSI Model, Network & routing protocols, WAN operations SecuritySSL, Cryptography, Firewall, VPN, DDoS & experience in network security exposure. Familiarity with Windows, MacOS, working knowledge of UNIX/Linux operating systems and commands Proficiency in cloud platforms such as AWS, Azure, or Google Cloud. Experience with containerization and orchestration technologies such as K8s and Docker. Experience with VMware, KVM or equivalent hypervisors. Experience with Salesforce service CRM system. API knowledge, Basic Programming/Scripting skills (Python, tcl, bash, JavaScript) Experience interacting with AI and prompting for questions. What You’ll Get: Hybrid working mode Career growth and development opportunities Recognitions and Rewards Employee Assistance Program Competitive pay, comprehensive benefits, and cool perks Culture of Giving Back Dynamic Diversity & Inclusion Interest Groups Apply if you believe your own unique capabilities can contribute to the success of this role and our organization! #LI-BH1 The About The Role is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change. Please note that F5 only contacts candidates through F5 email address (ending with @f5.com) or auto email notification from Workday (ending with f5.com or @myworkday.com ) . Equal Employment Opportunity It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability, marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws. This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. F5 offers a variety of reasonable accommodations for candidates . Requesting an accommodation is completely voluntary. F5 will assess the need for accommodations in the application process separately from those that may be needed to perform the job. Request by contacting accommodations@f5.com .

Skill Required: Delmia Apriso Experience Range in Required Skills: 4 to 6 years Job Description: DELMIA Developer, Enovia/3dx Exp, Knowledge in CAD and PLM Tools, Java, MQL, TCL, SQL

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience in timing analysis and physical design. Experience in one or more scripting languages, such as Perl, Tcl, Python. Preferred qualifications: Experience in physical design tool automation: synthesis, PandR tools. Experience in extraction of design parameters, QoR metrics and analyzing data trends. Experience in engineering across physical design and level implementation. Knowledge of timing signoff conditions and parameters. Understanding of parasitic extraction tools and flow. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Drive the physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to push PPA and yield. Analyze power performance area trade-offs across different methodologies and technologies. Work with cross-functional architecture, IPs, design, foundry, CAD and sign-off methodology teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

We are hiring DFT Engineer | Hyderabad Notice Period: 30 Days Position: DFT Engineer Looking for passionate professionals with 4 to 6 years of experience in Design for Test (DFT) to join our growing team in Hyderabad ! Key Responsibilities: Drive innovative DFT implementation at RTL and Gate level for SoC designs at both hard macro and chip top level, including: Scan insertion MBIST (Memory BIST) LBIST (Logic BIST) Boundary Scan Generate and validate ATPG patterns through simulation DFT verification using RTL and Gate-level simulations Collaborate with cross-functional teams across: Static Timing Analysis (STA) Synthesis Logic Equivalence Check (LEC) CLP Functional Verification & Validation Tool Proficiency: Experience with DFT tools from: Siemens Synopsys Cadence Technical Skills: Strong coding skills in: Verilog, VHDL C/C++ TCL, Perl, Python

Warm welcome from SP Staffing Services! Reaching out to you regarding permanent opportunity !! Job Description: Exp: 4-10 yrs Location: Chennai / Bangalore / Pune / Hyderabad Skill: Enovia Developer/Lead Required Technical Skill Set** Experience in platform upgrade , preferred 2019x to 2023x Proficient with 3D Experience product suite: Engineering central, Library central and document management, Change Management Expert in MQL, TCL, JPO Experience in developing the Enovia PLM system using configuration and customization (Trigger, UI level 3, JPO, JSP) Understand and execute the steps to upgrade Enovia V6/3D experience platform to targeted release. Experience in Rest Webservices. Good knowledge in Java, JSP, Java script, jQuery, Ajax, HTML JSON. XML SQL. Experience in customizing the Enovia V6 system using configuration and customization. Experience of using APIs. Experience in developing the interface of Enovia applications with different systems using APIs. Experience in Widget Development. Understanding of Unified product structure, Enterprise Change Management., 3DSearch. Strong knowledge of Technia components and TSO ., PNO and data securit Interested can share your resume to sangeetha.spstaffing@gmail.com with below inline details. Full Name as per PAN: Mobile No: Alt No/ Whatsapp No: Total Exp: Relevant Exp in Enovia : Rel Exp in MQL/TCL/JPO: Rel Exp in Customization: Current CTC: Expected CTC: Notice Period (Official): Notice Period (Negotiable)/Reason: Date of Birth: PAN number: Reason for Job Change: Offer in Pipeline (Current Status): Availability for virtual interview on weekdays between 10 AM- 4 PM(plz mention time): Current Res Location: Preferred Job Location: Whether educational % in 10th std, 12th std, UG is all above 50%? Do you have any gaps in between your education or Career? If having gap, please mention the duration in months/year:

Who We Are At Kyndryl, we design, build, manage and modernize the mission-critical technology systems that the world depends on every day. So why work at Kyndryl? We are always moving forward – always pushing ourselves to go further in our efforts to build a more equitable, inclusive world for our employees, our customers and our communities. The Role As a Disaster Recovery Manager at Kyndryl, you’ll solve complex problems and identify potential future issues across the spectrum of platforms and services. You’ll be at the forefront of new technology and modernization, working with some of our biggest clients – which means some of the biggest in the world. There’s never a typical day as a Disaster Recovery Manager at Kyndryl, because no two projects are alike. You’ll be managing systems data for clients and providing day-to-day solutions and security compliance. You’ll oversee a queue of assignments and work directly with technicians, prioritizing tickets to deliver the best solutions to our clients. One of the benefits of Kyndryl is that we work with clients in a variety of industries, from banking to retail. Whether you want to broaden your knowledge base or narrow your scope and specialize in a specific sector, you can find your opportunity here. You’ll also get the chance to share your expertise by recommending modernization options, identifying new business opportunities, and cultivating relationships with other teams and stakeholders. Does the work get challenging at times? Yes! But you’ll collaborate with a diverse group of talented people and gain invaluable management and organizational skills, which will come in handy as you move forward in your career. Your future at Kyndryl Every position at Kyndryl offers a way forward to grow your career, from Junior System Administrator to Architect. We have opportunities for Cloud Hyperscalers that you won’t find anywhere else, including hands-on experience, learning opportunities, and the chance to certify in all four major platforms. One of the benefits of Kyndryl is that we work with clients in a variety of industries, from banking to retail. Whether you want to broaden your knowledge base or narrow your scope and specialize in a specific sector, you can find your opportunity here. Who You Are You’re good at what you do and possess the required experience to prove it. However, equally as important – you have a growth mindset; keen to drive your own personal and professional development. You are customer-focused – someone who prioritizes customer success in their work. And finally, you’re open and borderless – naturally inclusive in how you work with others. Required Technical And Professional Experience Minimum exp 7 years of experience. Education qualification- Any Graduate. BCP-DR Application Architecture Your understanding customer IT-DR for On-Prime/Off-Prime/Hybrid Infrastructure for the application. Your understanding DR-DRILL to map them into Kyndryl Resiliency Orchestration solution (Sanovi DRM solution) Content Maintenance Perform updates, revisionsMaterials subject to maintenance include: LLD, HDL, Solution Design/Approach document, Technical Reports, PPTS etc. Experience in Linux and any database (Oracle, MySQL). Strong understanding of the Data Protection (Back-up & Recovery, BCP DR, Storage Replication, Database Native Replications, Data Archival & Retention) for application workloads such as MS SQL, Exchange, Oracle, VMware, Hyper-V, azure, AWS etc. Extremely good hands-on experience with Standalone and Clustered UNIX (AIX/Solaris/HPUX/RHEL/etc.) and windows platform. TCL/Shell/Batch/PowerShell/Expect Scripts or similar scripting languages is must. Should be able to write scripts to integrate with different technologies using CLI's /API's. Understand and strong knowledge of any Storage Replication technology with various DR Scenarios. Should be able to design/architect and build LLD, HLD, Implementation. Application testing experience may be added advantage Overall IT Infrastructure understanding is an added advantage Cyber (IT) Security related experience is an added advantage. Keep management and stakeholders informed about the status of disaster recovery preparedness, including risks, progress, and improvements. Preferred Technical And Professional Experience Hands on knowledge of Disaster recovery tool. Hands on experience on Linux administration and excellent scripting knowledge10 years of experience in Disaster recovery practice with experience in Banking, Manufacturing, Insurance and BFSI clients. Being You Diversity is a whole lot more than what we look like or where we come from, it’s how we think and who we are. We welcome people of all cultures, backgrounds, and experiences. But we’re not doing it single-handily: Our Kyndryl Inclusion Networks are only one of many ways we create a workplace where all Kyndryls can find and provide support and advice. This dedication to welcoming everyone into our company means that Kyndryl gives you – and everyone next to you – the ability to bring your whole self to work, individually and collectively, and support the activation of our equitable culture. That’s the Kyndryl Way. What You Can Expect With state-of-the-art resources and Fortune 100 clients, every day is an opportunity to innovate, build new capabilities, new relationships, new processes, and new value. Kyndryl cares about your well-being and prides itself on offering benefits that give you choice, reflect the diversity of our employees and support you and your family through the moments that matter – wherever you are in your life journey. Our employee learning programs give you access to the best learning in the industry to receive certifications, including Microsoft, Google, Amazon, Skillsoft, and many more. Through our company-wide volunteering and giving platform, you can donate, start fundraisers, volunteer, and search over 2 million non-profit organizations. At Kyndryl, we invest heavily in you, we want you to succeed so that together, we will all succeed. Get Referred! If you know someone that works at Kyndryl, when asked ‘How Did You Hear About Us’ during the application process, select ‘Employee Referral’ and enter your contact's Kyndryl email address.

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:- BTECH/MTECH Location: Bangalore & Noida Experience:- The Engineers with 5 to 10 years of Experience 2.Job description - Physical Verification- Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5 to 10 years of Experience Location:- Bangalore/ Noida

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! Job Title: Physical Verification Co-op Engineer Location: Bangalore Company: AMD India Pvt Ltd. About Us: AMD is at the forefront of the chip-making industry, dedicated to advancing technology through innovation and excellence in engineering. We are seeking a highly skilled Physical Verification Methodology Engineer to develop and enhance verification methodologies and support our design teams through successful tape-outs. THE ROLE: As a Physical Verification Methodology Engineer, you will be responsible for developing, implementing, and maintaining robust physical verification methodologies. You will collaborate with design teams to ensure smooth verification processes and provide support throughout the tape-out phase. Your role will be pivotal in enhancing the efficiency and reliability of our verification flows. THE PERSON: You are a team player who has excellent interpersonal skills and experience collaborating with other engineers located in different sites and timezones. You have strong analytical and problem-solving skills, willingness to learn and ready to take on problems. You are highly motivated to push the envelope and technically supervise the junior engineers within the team. KEY RESPONSIBILITIES: Develop and refine physical verification methodologies, including DRC, LVS, and ERC, to meet design requirements and industry standards. Provide comprehensive support to design teams, ensuring seamless integration of verification methodologies into the design flow. Assist in resolving complex verification issues and guide teams through debugging processes. Work closely with EDA tool vendors to enhance tool capabilities and address specific verification challenges. Automate verification processes through scripting and tool customization to improve efficiency and accuracy. Generate detailed documentation and training materials for design teams. Ensure compliance with industry standards and best practices in physical verification. Participate in tape-out reviews and provide critical feedback to ensure successful tape-outs. Qualifications: Master’s/Bachelor’s Degree in Electronics Engineering Extensive experience in physical verification and methodology development within the semiconductor industry. Proficiency with industry-standard verification tools such as Calibre, Mentor Graphics, or ICV , Synopsys. Strong debugging skills and in-depth knowledge of DRC/LVS/ERC methodologies. Experience with scripting languages (TCL, Perl, Python) for automation purposes. Excellent problem-solving abilities and attention to detail. Strong communication and collaboration skills. Preferred Experience: Knowledge of PowerVia and 3DStack concepts. Proven track record in supporting design teams through successful tape-outs. Familiarity with layout editing tools such as DesignREV and ICVWB Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10729 Date posted 04/22/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly. What You’ll Be Doing: Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. ing extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence. The Impact You Will Have: Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning. What You’ll Need: A Bachelor’s degree in Electrical/Electronics/Computer-Science Engineering with a minimum of 8 years of related experience, or a Master’s degree with 6 years of relevant experience. In-depth understanding of data structures, algorithms, and their applications. Excellent software development experience with C/C++ on UNIX/Linux platforms. Exposure to Python, TCL, and shell scripting languages is preferable. Exposure to HDL languages like Verilog or System Verilog is desirable, with a willingness to learn their nuances. Demonstrated history of good analytical, debugging, and problem-solving skills. Experience with complex and large software code-based tool development. Who You Are: You are a motivated and enthusiastic engineer who excels in both independent and collaborative settings. You have a solid desire to learn and explore new technologies, and you exercise good judgment in developing methods and techniques to meet project goals. Your excellent written and oral communication skills in English enable you to collaborate effectively and present your ideas clearly. Special consideration will be given to candidates with a background in hardware functional verification and/or synthesis techniques, as well as knowledge of software specification, design processes, and regression testing. The Team You’ll Be A Part Of: You will join the Hardware Assisted Verification team at Synopsys, a group of dedicated and innovative engineers focused on developing and enhancing our verification tools. Our team is committed to pushing the boundaries of technology and delivering high-performance solutions that meet the needs of our customers. We work in a collaborative and dynamic environment, where creativity and innovation are encouraged and valued. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10809 Date posted 04/21/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 4 -10 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E/ B.Tech/ M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10811 Date posted 04/21/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 4-10 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E/ B.Tech/ M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.