1597 Tcl Jobs - Page 26

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Educational Qualifications B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 10+ years of experience in physical design using industry EDA tools. Lead Sub System/SOC physical design for at least 1 product. Experience in Python/Perl/TCL programming languages. Experience in signoff domains (timing, IR-RV. Power, Layout Verification) is an added advantage. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Educational Qualifications B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Educational Qualifications B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 5+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Senior Principal / Principal / StaffPhysical Design Engineer - STA Bangalore (Hybrid ) / Hyderabad (Hybrid ) Company Background Introducing The Information’s 50 Most Promising Startups for 2024 We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Full Time \ Experienced Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device. Roles and Responsibilities Perform STA (static timing analysis) at block/full-chip level Specify timing ECOs either manually or via a tool-generated flow Perform noise analysis at the block/full-chip level Develop and debug timing constraints Define and implement MCMM (multi corner, multi-mode) timing closure methodology Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications : Proficient in STA tools like Tempus, Tweaker, and PrimeTime Proficient in programming languages like Tcl, python, etc. Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR Strong understanding of LVF/OCV variation methodologies and their implementation Knowledge of timing convergence in multi-voltage scenarios Working knowledge using timing derates and implementing timing derates into the flows Minimum BSEE/CE + 12 years or MSEE/CE 10+ years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Alternate Job Titles: Senior Staff AI Methodology Engineer Principal EDA Solutions Engineer AI-Driven RTL-to-GDS Flow Specialist Lead Application Engineer – AI EDA Solutions We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way. Your leadership skills are proven—whether guiding junior engineers, collaborating with global customers, or interfacing with R&D to influence product direction. You communicate complex concepts with clarity, and your presentations inspire confidence and trust. Adaptable and resourceful, you excel at managing multiple priorities in dynamic, fast-paced environments. You have a track record of technical excellence, a commitment to continuous learning, and a genuine enthusiasm for empowering others. If you are driven by solving tomorrow’s silicon challenges and have a curiosity to explore new AI-driven design paradigms, you will find your next career milestone here at Synopsys. What You’ll Be Doing: Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries. Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs. Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation. Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges. Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables. Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement. The Impact You Will Have: Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results. Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development. Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation. Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market. Elevate the technical capabilities of the application engineering team through mentorship and cross-training. Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with10+ years of relevant experience. Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar). Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes. Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies. Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment. Outstanding verbal and written communication, presentation, and customer interaction skills. Who You Are: Collaborative and empathetic leader, skilled at building relationships and enabling the success of others. Analytical thinker with a problem-solving mindset and a passion for continuous improvement. Adaptable and resilient in the face of evolving customer requirements and technology landscapes. Strong organizational skills, able to manage multiple projects and priorities with poise. Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design. The Team You’ll Be A Part Of: You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description: We are seeking a Physical Design Lead with strong expertise in RTL-to-GDSII flow for advanced technology nodes (7nm and below). The role involves leading SoC/IP physical implementation, driving PPA goals, and ensuring successful tapeouts. You will manage a team, interface with cross-functional groups, and own block/top-level execution. Key Skills: Floorplanning, Placement, CTS, Routing, Signoff STA, IR/EM, Power & Physical Verification EDA tools: Innovus, PrimeTime, Calibre, etc. Scripting (TCL/Perl/Python), UPF, ECOs Strong leadership & communication skills

Job Description In your new role you will: Contribute to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design. Work independently in different phases of the RTL2GDS flow with focus on Synthesis and Constraining for efficient Timing Closure, Equivalence check, PnR closure, IR/EM analysis and fixing along with physical checks cleanup sign-off Work with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow. Focus on PPA, define the Partition shapes, pins and feedthrough along with IP integration guidelines are followed (reviewed along with IP owners) to suit the requirements. Analyze and solve problems of high complexity using your global expert network Drive the PnR closure of multimillion gate designs in lower technology nodes, perform SoC level IR/EM analysis, debugging and fixing. Running SoC level Physical verification, debugging and fixing including Chip finishing, metal fill, Sealring and Tapeout checks Be a member of an expert network and drive innovation, methodology for the RTL to GDS2 development cycle of next generation automotive SoCs. Your Profile You are best equipped for this task if you have: A degree in Electrical Engineering, Microelectronics or a similar field. At least 6 of experience in Physical Design of highly complex SoCs. Experience in RTL coding, IP issues and handling is plus. Programming skills and knowledge in scripting languages like Tcl, Perl or Python. Experience in working as a member of SoC design teams with high cost and quality awareness. Fluent English language skills – with German being an added plus. Understanding of industry standard tools for physical design and signoff Be a quick learner and team player while taking and acting on responsibilities Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Job Title: Formal Verification Engineer Location: Bangalore Experience: 4+Years Job Type: Full-time Industry: Semiconductor / ASIC Design / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and SoC designs. Key Responsibilities: Define and implement formal verification strategies and plans. Develop formal properties and assertions for critical design blocks. Apply formal techniques such as property checking, sequential equivalence checking , and formal coverage. Analyze formal results, identify unreachable or vacuous properties, and refine models. Collaborate closely with RTL designers, DV engineers, and architects. Integrate formal into overall verification methodology and sign-off. Document and present formal verification methodologies, assumptions, and results. Required Skills: 4+ years of experience in formal verification using industry tools (e.g., JasperGold, VC Formal, Questa Formal, OneSpin). Strong knowledge of SystemVerilog Assertions (SVA) and formal property specification. Solid understanding of digital design concepts and RTL coding in Verilog/SystemVerilog. Familiar with formal coverage metrics and convergence techniques. Experience in debugging complex design bugs using formal tools. Ability to abstract and model designs or protocols at different levels. Desirable Skills: Familiarity with safety-critical designs (ISO 26262, DO-254) is a plus. Knowledge of common protocols: AXI, AHB, PCIe, Ethernet, etc. Exposure to sequential equivalence checking and abstraction modeling. Understanding of simulation-based verification and integration with formal. Proficiency in scripting (Python, Perl, or TCL) for automation. Interested can Share CV to sharmila.b@acldigital.com

Job Title: Design Verification Engineer Exp Level:4+yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design bugs. Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug. Protocols: Verify IP/SoC-level designs for common protocols (AXI, APB, PCIe, DDR, etc.). Automation: Develop scripts (Python/Perl/TCL) to improve verification efficiency. Documentation: Maintain verification reports and review results with stakeholders. Compliance: Ensure adherence to project timelines and quality standards. Interested can share CV to sharmila.b@acldigital.com

Job Description Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL synthesis and constraints generation/validation for MCU SoCs, ensuring they meet performance, power, and area specifications Develop and implement innovative implementation methodologies and tools to enhance productivity and design quality Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues Conduct thorough design reviews and provide constructive feedback to peers and junior engineers Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA Support Low Power Implementation Support formality checks Preferred Experience Experience in owning RTL synthesis and constraints for complex IPs/SS/SoC Experience in owning or supporting STA at full-chip level Exposure to latest methodologies in constraints generation, promotion/demotion and validation Familiarity with Low Power Implementation flows Qualifications Required and Preferred Qualifications Required: Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE degree and 12+ years of experience in IC design, or MSEE (or PhD) with 9+ years of experience and with a proven track record of delivering high-quality designs Experience with industry-standard EDA tools for synthesis, constraints validation and static timing analysis Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Ability to mentor and guide junior engineers in IC design best practices and methodologies Scripting experience in Shell, Perl, Python and TCL is a plus Good communication skills for interacting between different design groups cross functional groups are required Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Some level of understanding of DFT flows and steps Exposure to Automotive SoC designs Additional Information Soft Skills and Cultural Fit Exceptional problem-solving skills with the ability to analyse complex design challenges Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required: Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints Additional Information Soft Skills and Cultural Fit Strong communication skills to articulate design concepts and collaborate with multi-disciplinary teams Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Hi, Greetings from ACL Digital, Looking for CPU Verification Engineers Exp level: 4+years Location: Banglore Job Description: We are seeking a skilled and motivated CPU Verification Engineer to join our microprocessor verification team. In this role, you will contribute to the verification of high-performance, low-power CPU cores by developing scalable testbenches, driving complex test scenarios, and ensuring full functional coverage and quality sign-off Responsibilities: 1.Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. 2.Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. 3.Working with project management and leads on planning tasks, schedules, and reporting progress 4.Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Qualifications: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering 4+ years of relevant experience in CPU or SoC-level functional verification Interested can CV to sharmila.b@acldigital.com

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Design Responsibilities Architecture exploration Micro-architecture development Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience with Verilog or System Verilog Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization Preferred Qualifications 15+ years of experience in silicon development Experience in data path development Experience in CPU, NOC (Network on Chip), Memory and Peripheral Subsystems Experience in HLS (High-Level Synthesis) Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting) Experience working across multiple projects About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

We are seeking highly motivated and talented VLSI Engineers with 2-4 years of industry experience to join our intensive Campus Training Program. This program is designed to provide in-depth, hands-on training in various aspects of VLSI design, verification, and implementation, specifically tailored to align with our current projects and future technological advancements. Upon successful completion of the training, candidates will transition into key roles within our VLSI design teams. This is an excellent opportunity for engineers looking to deepen their expertise, specialize in cutting-edge VLSI methodologies, and contribute to the development of next-generation semiconductor products. Responsibilities during the Training Program: * Actively participate in structured training modules covering advanced VLSI concepts, methodologies, and tools. * Engage in hands-on lab sessions and practical exercises to apply learned concepts. * Collaborate with trainers and mentors on assigned projects and case studies. * Complete individual and group assignments, demonstrating understanding and proficiency in VLSI sub-domains. * Participate in technical discussions, design reviews, and knowledge-sharing sessions. * Learn and adhere to industry best practices, design flows, and quality standards. * Continuously seek to improve technical skills and knowledge through self-study and provided resources. * Document progress, learning outcomes, and project work thoroughly. Key Areas of Training (may include, but are not limited to): * Digital IC Design: Advanced RTL design, low-power design techniques, clock domain crossing (CDC). * Verification: Advanced UVM/SystemVerilog methodologies, functional coverage, formal verification. * Physical Design: Floorplanning, placement, routing, clock tree synthesis (CTS), static timing analysis (STA), power integrity (PI) analysis. * Design for Testability (DFT): Scan insertion, ATPG, boundary scan. * Analog/Mixed-Signal Design (if applicable): Device physics, circuit simulation, layout considerations. * Front-End Tools: Synthesis, Linting, STA. * Back-End Tools: Place and Route, DRC/LVS. * Scripting: Perl, Python, TCL for automation. * EDA Tools: Exposure to industry-standard EDA tools from Cadence, Synopsys, Mentor Graphics (specific tools will be taught based on company needs). Required Qualifications: * Bachelor's or Master's degree in Electronics and Communication Engineering (ECE), Electrical Engineering (EE), or a related field. * 2-4 years of professional experience in VLSI design, verification, or physical design. * Strong fundamental understanding of digital electronics, circuit theory, and semiconductor physics. * Proficiency in at least one hardware description language (HDL) such as Verilog or VHDL. * Familiarity with the VLSI design flow (front-end to back-end). * Experience with scripting languages (e.g., Python, Perl, TCL) is highly desirable. * Excellent problem-solving and analytical skills. * Strong communication and interpersonal skills. * Ability to learn quickly and adapt to new technologies and methodologies. * Self-motivated with a strong desire to build a long-term career in VLSI. Preferred Qualifications (Assets): * Prior experience with specific EDA tools (Cadence Virtuoso, Synopsys DC/ICC/VCS, Mentor Graphics Calibre, etc.). * Experience with UVM methodology for verification. * Understanding of low-power design techniques. * Familiarity with formal verification concepts. * Exposure to advanced technology nodes.

Hello Everyone!!! We are seeking WLAN Test Engineer with 3 to 8 years of Experience for the Position in Bangalore, Chennai and Hyderabad. Candidates who can start immediate or within 30 Days are preferred. Interested individuals or referrals can share profile with us. Below the JD:- Sound knowledge WLAN IEEE802.11 a/b/g/n/ac/ax Test experience with minimum of 3 to 8 years Ethernet & Wired networking (added advantage) Independent Project handling with analytical ability Testing Experience Functional / Performance / IOT / Certification WLAN tests Protocols/Layers with good theoretical & practical knowledge Sound knowledge on Layer 1, 2, 3, IEEE802.11 a/b/g/n/ac/ax Knowledge on WPA2/WPA3, MU-MIMO, OFDMA, Beamforming, Roaming etc Traffic Generators Understating. Key Skills: Traffic Analyzers Wireshark, Ethereal, airopeak/omnipeak Operating Systems Windows 10/XP/Win7, Linux Automation Scripting Knowledge of Automation Scripts is mandatory – Python / Perl / TCL WLAN Testing SKILLS TOOLS/Protocols Technologies with sound knowledge WLAN IEEE802.11 a/b/g/n/ac/ax Test. Knowledge on RFC2544, RFC2889, RFC3918 tests etc. Traffic Analyzers Wireshark, Ethereal, airopeak/omnipeak Operating Systems Windows 10/XP/Win7, Linux Automation Scripting Knowledge of Automation Scripts is mandatory – Python / Perl / TCL.

Job Description Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints Additional Information Soft Skills and Cultural Fit Strong communication skills to articulate design concepts and collaborate with multi-disciplinary teams Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL synthesis and constraints generation/validation for MCU SoCs, ensuring they meet performance, power, and area specifications Develop and implement innovative implementation methodologies and tools to enhance productivity and design quality Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues Conduct thorough design reviews and provide constructive feedback to peers and junior engineers Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA Support Low Power Implementation Support formality checks Preferred Experience Experience in owning RTL synthesis and constraints for complex IPs/SS/SoC Experience in owning or supporting STA at full-chip level Exposure to latest methodologies in constraints generation, promotion/demotion and validation Familiarity with Low Power Implementation flows Qualifications Required and Preferred Qualifications Required Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE degree and 12+ years of experience in IC design, or MSEE (or PhD) with 9+ years of experience and with a proven track record of delivering high-quality designs Experience with industry-standard EDA tools for synthesis, constraints validation and static timing analysis Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Ability to mentor and guide junior engineers in IC design best practices and methodologies Scripting experience in Shell, Perl, Python and TCL is a plus Good communication skills for interacting between different design groups cross functional groups are required Preferred Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Some level of understanding of DFT flows and steps Exposure to Automotive SoC designs Additional Information Soft Skills and Cultural Fit Exceptional problem-solving skills with the ability to analyse complex design challenges Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Role & responsibilities The MES-PLM 3Dex developer will be part of the IT Digital Continuity department (CDN), responsible for MES and PLM customization maintenance and support business applications and services. 1. Work directly with functional consultants and solution architects to implement, maintain and support key software solutions using PLM 3D Experience (APRISO, ENOVIA) developement tools 2. Provide support for these solutions and your own developments 3. Proactively reach out to your clients and peer developers, sit next to them, and understand their needs and requirements without Business Analysts 4. Build trust-based relationships with your colleagues and clients Preferred candidate profile Minimum 5 years of PLM experience. At least 2 Full Life Cycle Implementations/ Roll- Outs experience. Exposure to Ticketing Tool like Service Now is an added advantage.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Board bring-up activities for Software components like bootloader, platform managers, Linux Kernel, Linux drivers, Baremetal drivers and applications for ARM based boards. Testing, Verification bring up of Linux Kernel and Linux Drivers I2C, Flashes, USB , Ethernet, PCIe , DDR memory Tests etc. Develops and executes test plans to evaluate functionality, security, and efficiency of firmware utilizing emulation and evaluation boards for pre-silicon and post silicon verification. Analyzes, tracks, and debugs testing failures to determine corrective measures. Collaborates directly with the development team to assess test plan requirements and resolve failures. Run the Regression tests, triage issues, create Defects in the system and work with development team for closure. Automate and the functional and System level tests using Python and integrate the same in Test Automation framework and maintain the Test artifacts for any updates in the Test cases or in Test framework SkillsMust have Candidate should have 4-7yrs experience Working experience in verification and testing of Linux based Embedded System software etc. Good experience in Linux Device Driver Verification and validation on Linux, Bare metal, Real Time Operating Systems. Skills in compiling/building/cross-compiling, debugging, testing, deploying Bootloader, TF-A, Linux Kernel, Device tree, Middleware software, and BareMetal application images for board bring up activities through JTAG debuggers & Emulators using different boot modes Good understanding of any one of SoC/Processing Technologies like ARM/RISC-V/X86, MMU, Interrupt handling, Caches etc. Hands on with one or more peripherals/controllers like UART, I2C, SPI, USB, SD, eMMC, QSPI, PCIe etc. Define, Design and Develop manual/Automation test cases for Embedded system projects Programming skills in C/C++, Makefile, Linker file creation, scripting language Python/Shell/Tcl Experience in GIT environment and Test Automation framework Pytest, Jenkins etc. Good to have exposure in design tools like VIVADO, VITIS, Configuration management tools like GIT/Perforce, JIRA, Confluence etc. Nice to have Education B.E/B.Tech or M.E/M.Tech in Electronics & Communications or Computer Science

For sub system in high performance microprocessor design, you are responsible for Timing constraintmodelling given timing specification, generation, validation. Design timing data generation, validation, timing data analysis. Driving timing convergence across different timing corners , by working with logic, circuit, integration designers. Ensuring quality and efficiency in timing convergence. Engaging in automation of flow, data analysis. Required education Bachelor's Degree Required technical and professional expertise 5+ years of industry experience Hands on experience in static timing analysis, modelling timing constraints, setting up timing environment and timing runs, data analysis, timing fix implementation, timing ECO generation. Knowledgeable in physical design flow, logic. Experience with timing fixes (slack, electrical, noise). Preferred technical and professional experience Require programming skills with any language PYTHON, PERL , and/or TCL .

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Experience Level:5+ years of RTL design and development Location: Hyderabad/Bangalore Job Description:Silicon Design Engineer Basic Job Deliverable:Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification, design, user-guide, etc., o Experience:  Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools  Experience with Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc.  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Qualification:B.Tech/M.Tech (CSE/ECE/EEE) Interested can share CV to sharmila.b@acldigital.com

Experience Level:5+ years of RTL Verification Location: Hyderabad/Bangalore Job Description:Hardware Verification Engineer Basic Job Deliverable:HW Verification Engineer o Responsible for RTL verification, developing Develop SV/UVM testbenches at Top/Sub-system/Block-levels. o Responsible for driving test plan and test spec development and execution, generating documents, such as user-guide, test plan, test spec, test report etc., o Engaging in verification environment architecture and methodology development. o Experience:  Experience in System Verilog and UVM programing  Experience with verification of protocols like Ethernet/PCIe/SPI/I2C/USB  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc. Experience with Xilinx technology and tools, FPGA verification and test  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Qualification:B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Interested can share CV to sharmila.b@acldigital.com

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).