Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Additional About The Role : General Summary We"™re looking for a frontend CAD developer to produce scalable software solutions for in-house EDA flows. As part of a cross-functional team, you"™ll be responsible for the full software development life cycle, from conception to deployment. Must have hands-on experience in developing the large software systems with structured development cycles. Should have good problem-solving skills, strong communication skills and a flair to work in a challenging environment Education B.E/B.Tech or M.E/M.Tech in VLSI/EE/EC/Computer Science Skills/Experience: 8 years of experience in EDA Tool/Flow Development, Deployment and Support Strong experience in Scripting languages like Perl, Tcl, Python, GUI development on Linux platform Should be well versed with VLSI frontend Design/Verification steps, RTL/System Verilog and UVM methodologies Knowledge of Clearcase Perforce, GIT, Makefiles Database design, Computer Architecture is a plus Desirable Scripting and automation skills:Unix/Linux shell programming, Perl/Python, Makefile Should be sincere, fast learner, committed, having good communication skills, and willing to take up new challenge

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment. Education Requirements Required:Bachelor's, Electrical Engineering or equivalent experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional About The Role : Minimum Qualifications Bachelor's degree in Science, Engineering or closely related field Experience with digital design and RTL development, Experience with front end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime Preferred Qualifications Knowledge and experience of graphics design and development Proficient in Perl, TCL and shell scripting Excellent interpersonal and team skills yet able to work independently and able to problem solve complex, unique and detailed issues Be Familiar with The latest EDA tools for synthesis, formal verification, timing analysis and physical design

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 5+ years Hardware Engineering experience or related work experience. 4+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor"™s or Master"™s degree from a top-tier institute. 2- 5 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job Requirements: Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5 to 7 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience :6+ years(A Must) Implementation with emphasis on Physical Verification & Hard macro/core finishing activities. Must have led and been primarily responsible for physical verification checks , fixing and sign-off. Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Deep understanding of ESD, latch-up etc. Own and execute PV activities at the Top/Block level. Work closely with PD team in addressing their PV issues and suggest solutions to them. Work with CAD team in refining the existing flows/methodologies and to resolve the issues. Experience in IO, Bump planning and RDL routing Strategy is a plus. Develop and implement timing and logic ECOs is a plus Innovus/FC level DRC fixing is a plus Python, PERL/TCL knowledge is a plus. Ability to plan and work independently and coordinate with cross-functional teams Has ability to close sign off DRC based on PNR markers is plus Skill Set: Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. Good overall understanding of the Custom IC design flow. Good understanding of layouts and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. People management /Floorplanning/Power Planning/PDN experience is BIG Plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 15+ years Hardware Engineering experience or related work experience. 14+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 4+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary We"™re looking for a frontend CAD developer to produce scalable software solutions for in-house EDA flows. As part of a cross-functional team, you"™ll be responsible for the full software development life cycle, from conception to deployment. Must have hands-on experience in developing the large software systems with structured development cycles. Should have good problem-solving skills, strong communication skills and a flair to work in a challenging environment Education B.E/B.Tech or M.E/M.Tech in VLSI/EE/EC/Computer Science Skills/Experience: 8 years of experience in EDA Tool/Flow Development, Deployment and Support Strong experience in Scripting languages like Perl, Tcl, Python, GUI development on Linux platform Should be well versed with VLSI frontend Design/Verification steps, RTL/System Verilog and UVM methodologies Knowledge of Clearcase Perforce, GIT, Makefiles Database design, Computer Architecture is a plus Desirable Scripting and automation skills:Unix/Linux shell programming, Perl/Python, Makefile Should be sincere, fast learner, committed, having good communication skills, and willing to take up new challenges

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Role * Familiar with Physical Design Life cycle of chip development, especially Floorplanning and PnR * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them* Provide tool support and issue debugging services to physical design team engineers across various sites* Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools* Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory* Basic understanding of Timing/Formal verification/Physical verification/extraction are desired* Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are seeking a dedicated and skilled EM/IR Methodology Engineer to join our team. The role involves developing and maintaining methodologies for Electromigration (EM) and Voltage Drop (IR) analysis to ensure robust and reliable designs in advanced semiconductor technologies. The ideal candidate will work closely with cross-functional teams to optimize power delivery networks and ensure design compliance with EM/IR standards. Key Responsibilities: Develop, validate, and optimize methodologies for Electromigration (EM) and Voltage Drop (IR) analysis for advanced semiconductor designs. Collaborate with design, CAD, and physical implementation teams to optimize power delivery networks. Enhance and automate workflows to improve PDN analysis efficiency. Partner with EDA tool vendors to enhance and customize EM/IR analysis tools. Support design teams in EM/IR verification and sign-off. Required Skills and Qualifications: Bachelor"™s or Master"™s degree in Electronics, Electrical Engineering, or a related field. 3-5 years of experience in EM/IR analysis or physical design methodology. Strong understanding of Electromigration (EM) and Voltage Drop (IR) concepts and their impact on circuit reliability. Hands-on experience with EM/IR analysis tools such as Voltus , RedHawk , Totem , or equivalent. Preferable if worked on 2.5D/3D-IC , CoWoS technologies. Exposure to AI/ML concepts will be bonus. Proficiency in scripting languages such as Python , Perl , or Tcl to automate workflows. Good understanding of STA concepts. Strong problem-solving and analytical skills. Excellent communication and teamwork skills.

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1 to 3 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Project Role : Sales Capture Practitioner Project Role Description : Shape, sell and close deals that are single or multi service. Shephard the deal to develop the win strategy, the negotiation strategy, and the close plan. Must have skills : Sales Pursuit Management Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Sales Capture Practitioner, you will shape, sell, and close deals that are single or multi-service. Shephard the deal to develop the win strategy, the negotiation strategy, and the close plan. Be involved in the entire deal lifecycle from start to finish, ensuring successful outcomes. Roles & Responsibilities: Expected to be an SME, collaborate and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Expected to provide solutions to problems that apply across multiple teams. Lead the development of win strategies for deals. Create and execute negotiation strategies for successful deal closures. Manage and oversee the entire deal lifecycle. Provide guidance and mentorship to junior team members. Professional & Technical Skills: Must To Have Skills:Proficiency in Sales Pursuit Management. Strong understanding of sales methodologies and techniques. Experience in developing and executing sales strategies. Excellent communication and negotiation skills. Ability to analyze market trends and customer needs. Additional Information: The candidate should have a minimum of 12 years of experience in Sales Pursuit Management. This position is based at our Pune office. A 15 years full-time education is required. Qualifications 15 years full time education

Project Role : Sales Capture Practitioner Project Role Description : Shape, sell and close deals that are single or multi service. Shephard the deal to develop the win strategy, the negotiation strategy, and the close plan. Must have skills : Sales Pursuit Management Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Sales Capture Practitioner, you will shape, sell, and close deals that are single or multi-service. Shephard the deal to develop the win strategy, the negotiation strategy, and the close plan. Be involved in the entire deal lifecycle from start to finish, ensuring successful outcomes. Roles & Responsibilities: Expected to be an SME, collaborate, and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Expected to provide solutions to problems that apply across multiple teams. Lead the development of win strategies for deals. Create and execute negotiation strategies for successful deal closures. Manage and oversee the entire deal lifecycle. Provide guidance and mentorship to junior team members. Professional & Technical Skills: Must To Have Skills:Proficiency in Sales Pursuit Management. Strong understanding of sales methodologies and techniques. Experience in developing and executing sales strategies. Excellent communication and negotiation skills. Ability to analyze market trends and customer needs. Additional Information: The candidate should have a minimum of 12 years of experience in Sales Pursuit Management. This position is based at our Hyderabad office. A 15 years full-time education is required. Qualifications 15 years full time education

Experience: 5 + - Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPG generation & Simulations along with Pattern Porting/re-targeting and Coverage improvement -Experience with Scan, Compression, ATPG and simulations with Synopsys EDA tools. - Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team work skills

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience 8 years of experience in Emulation, FPGA Prototyping, or Validation domains 4 years of experience in people management, developing employees Experience in emulation/FPGA/simulation model build flows, model bring-ups and debugging Experience with industry standard emulation/FPGA prototyping platforms (e g , Palladium, Zebu, Veloce, Protium, HAPs, etc ) Preferred qualifications: 3 years of experience leading an emulation or FPGA prototyping team Experience with EDA debug tools (e g Verdi, SimVision/Indago, GDB) and SoC architecture and interfaces (e g , DDR, PCIe, etc ) Experience programming and scripting in C, C++, Python, Perl, or TCL Experience validating (or enabling) emulation friendly models in a Design Verification (DV) environment and bringing up bare-metal software on SoCs Experience in working with firmware/software teams to define model configurations to enable early software development Understanding of RTL to Emulation/FPGA flows including Emulation test benches (e g , Transactors/Accelerated VIPs, Hybrid, In-circuit Emulation) About The Job In this role, youll work to shape the future of AI/ML hardware acceleration You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications Youll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems In this role, you will help design, verify, and deploy ASIC projects through emulation based prototyping You will work directly with other emulation prototyping team members as well as designers, Design Verification (DV) engineers, Silicon Validation engineers, and Software teams to deliver emulation based prototyping capabilities for our ASIC projects, including compiling projects managing our prototyping platforms, debugging issues in infrastructure and design, and assisting in the hardware and lab bring up and validation of our ASIC systems Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them We keep our networks up and running, ensuring our users have the best and fastest experience possible Responsibilities Build, manage and lead the team responsible for full chip emulation/FPGA prototyping of complex AI/ML SoC designs and deliver to multiple customers such as software, firmware, platform, and post-silicon validation teams Lead and enable the team to bring up system level emulation models through reset, boot, and bare metal content or OS Influence the design and verification teams to enable emulation friendly model development Work with architects, designers, software engineers, preand post-silicon verification engineers to develop and review test plans, coverage, and reproduce failures on emulation Lead the development, execution, and debugging of full-chip/SoC tests on emulation platforms Explore new verification and emulation methodologies and implement them Drive all the people management functions including, but not limited to, hiring, people development, prioritizing and managing resources to achieve project execution timelines Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Satven hiring for CAE TCL/TK Engineer Job Location: Chennai. Experience: 3 Years to 8 Years. Skill Set: TCL/TK, Hypermesh, Hyperworks Notice Period: Immediate to 30 days. Job Description: CAE Automation Engineer Good knowledge of CAE processes. Autonomous in writing macros for Hypermesh, Hyperworks. Good command in TCL/TK Scripting. Ability to create executable files & creation for interactive GUI creation. Technical exchanges and communications with concerned teams. Interested and suitable profiles can share their resume to kumar_munusamy@satven.com

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description As Technical Lead – Design Verification, you will be the key contributor of ORAN SoC product design verification team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 10+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space. Key Responsibilities Develop testbench environment to perform verification of the design at IP/ Subsystem and SoC Level using SystemVerilog and UVM. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS. 10 or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off. Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch. Proficient in SystemVerilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing. Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB, , PCIe, PIPE interface, Serdes, UART, SPI, I2C, QSPI, DMA etc). Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus. Track record of successfully executing block or chip-level verification plans. Excellent communication and presentation skills, energetic and self-motivated. Work effectively with an off-site/ offshore design and verification teams across locations. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9901 Date posted 03/18/2025 Alternate Job Titles: Senior Verification Engineer, IP Verification Specialist, RTL Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated professional with a passion for design verification in the semiconductor industry. With a solid foundation in Electrical/Electronic Engineering, Computer Engineering, or Computer Science, you possess 4 to 8 years of hands-on experience in IP/SOC verification domains. Your expertise in industry-standard EDA tools, fault injection methods, and diagnostic coverage techniques sets you apart. You excel in creating test environments from functional specifications using methodologies like UVM/VMM/OVM and are proficient in advanced languages such as Verilog and System Verilog. Your strong analytical skills enable you to identify safety gaps in designs, ensuring robust and reliable IP cores. As an excellent communicator, you collaborate effectively with international teams, driving innovation and achieving project milestones. Your ability to work independently, precisely, and generate quality documentation makes you a valuable asset to our team. Experience with ISO26262 developments, fault injection, and scripting languages like Perl, TCL, or Python would be highly advantageous. What You’ll Be Doing: Developing design verification solutions for RTL-based IP Cores implementing complex protocols. Collaborating with architects, designers, and verification team members across multiple international sites. Performing fault injection on IP/SOC RTL designs to identify and address safety gaps using FMEDA data. Creating and running test environments from functional specifications using UVM/VMM/OVM methodologies. Analyzing fault lists and developing test cases for fault injection to achieve diagnostic coverage. Debugging designs in simulation and providing verification solutions for productivity, performance, and throughput improvement. The Impact You Will Have: Ensuring the reliability and safety of IP Cores used in automotive end-customer applications. Contributing to the development of high-performance silicon chips that drive innovation in the semiconductor industry. Enhancing the diagnostic coverage and safety standards of our IP designs. Improving the overall efficiency and performance of our verification processes. Collaborating with global teams to achieve project milestones and deliver high-quality IP solutions. Driving continuous technological innovation in the verification domain. What You’ll Need: Degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. 4 to 8 years of experience in IP/SOC verification domains. Hands-on knowledge of fault injection methods and diagnostic coverage techniques. Proficiency in Verilog, System Verilog, and debugging designs in simulation. Experience with UVM/VMM/OVM methodologies and creating test environments from functional specifications. Who You Are: An independent and precise worker with a drive for innovation. An excellent communicator with strong documentation skills. A collaborative team player who excels in problem-solving. Ideally experienced in ISO26262 developments and fault injection. Knowledgeable in C/C++, Shell, and scripting languages like Perl, TCL, or Python. The Team You’ll Be A Part Of: You will be part of the IP Group at Synopsys, working with a talented team of architects, designers, and verification engineers across multiple international sites. Our team focuses on developing robust and reliable IP Cores for automotive applications, driving innovation and ensuring the highest standards of safety and performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.