1597 Tcl Jobs - Page 33

Build backend services, automation scripts, and APIs using Python. Strong coding skills and experience with frameworks like Django or Flask.

Develop automation scripts and tools using Python to streamline business processes and testing.

Develop automation scripts and tools using Python to streamline business processes and testing.

Design and implement network security solutions including firewalls, VPNs, IDS/IPS, and security policies to safeguard IT infrastructure.

Employee type : C2H Must have experience in Various Performance Test Tools (like JMeter, LoadRunner, etc.). Functional, GUI and integration testing Need to have good communication skills

Notice Period: Immediate Joiners Employee type : C2H Minimum of 7 years of SAP ABAP experience Minimum 4 years of ABAP HR experience Good knowledge of HCM functional areas Should have worked in support engagements Location: Mumbai from client location Very good communication and flexible to work in shifts Also need good hands on experience in web dynpro , workflow and employee portal (Ess/Mss)

Skill: SAP MM with WM Notice Period: Immediate Joiners Job Description: Must Have Experience on SAP MM Should have Experience in WM as well Need to Have good Communication Skills

Advanced ABAP OO, Knowledge on Enterprise Services(Proxy Objects). Basic Functional knowledge of SD, MM and FI processes in SAP OOPS, CDS

Job Details: Skill: SAP Successfactor Notice Period: Immediate Joiners Job Description: Must Have Experience on SAP Successfactor Need to Have good Communication Skills

To perform activities associated with one or more software engineering lifecycle phases Principal Accountabilities: Understand customer requirements and suggest solutions or alternatives Fill timesheets and complete invoicing process on or before the deadline Engage with customer teams on an ongoing basis on all aspects of project delivery Seek informal feedback and escalate any issues to seniors in the team Develop software code as per specifications, by understanding customer requirements Track open tickets/ incidents in queue and allocate tickets to resources Constantly review if there is a better way of doing things, which may help with economising time or money or deliver better to the customer Perform code reviews as per standards and provide timely status update Monitor and track defects and manage any change requests Participate in quality reviews and implement quality norms Build reusable components and participate in review processes Develop and review project consolidated status reports Perform all activities related to maintaining successful knowledge management, including re usage, accuracy and efficiency Promote team work, motivate, mentor and develop subordinates Provide application production support as per process/RACI (Responsible, Accountable, Consulted and Informed) Matrix

Synthesis and Timing engineer to participate in the development of large SOCs with multiple physical blocks and 300+ clock domains. He/She must be high energy candidate with strong written and verbal communication skills, technically strong to find solutions and help the team both inside and outside the organization. REQUIRED SKILLS: RTL Design Quality checks, mainly Lint Automation using Python and TCL 5years+ experience, so not an NCG KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask and grasp new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. ACADEMIC CREDENTIALS: Bachelor's degree or Masters degree with 5years+ experience.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. 4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. 5. Debug and resolve test-related issues in simulation, silicon validation, and production. 6. Work closely with the physical design team to implement scan and clock constraints for timing closure. 7. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. 8. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 2-10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG. 3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent. Proficiency in 4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl). 5. Solid understanding of STA concepts and constraints related to DFT. 6. Experience in debugging silicon and ATE test patterns. Knowledge of test standards like IEEE 1149.x (JTAG) and 1500. 7. Excellent problem-solving skills and ability to work in a collaborative environment. Preferred Qualifications: 1. Experience with low-power DFT techniques. 2. Familiarity with fault diagnosis and yield improvement methodologies. 3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. 4. Knowledge of machine learning or AI techniques for test optimization. 5. Hands-on experience with multi-core and hierarchical DFT architectures. Why Join Us? 1. Be part of a team driving innovation in the semiconductor industry. 2. Work on challenging and impactful projects in a supportive environment. 3. Opportunities for career advancement and skill development. 4. Competitive salary and comprehensive benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

To perform activities associated with one or more software engineering lifecycle phases Principal AccountabilitiesUnderstand customer requirements and suggest solutions or alternatives Fill timesheets and complete invoicing process on or before the deadline Engage with customer teams on an ongoing basis on all aspects of project delivery Seek informal feedback and escalate any issues to seniors in the team Develop software code as per specifications, by understanding customer requirements Track open tickets/ incidents in queue and allocate tickets to resources Constantly review if there is a better way of doing things, which may help with economising time or money or deliver better to the customer Perform code reviews as per standards and provide timely status update Monitor and track defects and manage any change requests Participate in quality reviews and implement quality norms Build reusable components and participate in review processes Develop and review project consolidated status reports Perform all activities related to maintaining successful knowledge management, including re usage, accuracy and efficiency Promote team work, motivate, mentor and develop subordinates Provide application production support as per process/RACI (Responsible, Accountable, Consulted and Informed) Matrix

To perform activities associated with one or more software engineering lifecycle phases Principal AccountabilitiesUnderstand customer requirements and suggest solutions or alternatives Fill timesheets and complete invoicing process on or before the deadline Engage with customer teams on an ongoing basis on all aspects of project delivery Seek informal feedback and escalate any issues to seniors in the team Develop software code as per specifications, by understanding customer requirements Track open tickets/ incidents in queue and allocate tickets to resources Constantly review if there is a better way of doing things, which may help with economising time or money or deliver better to the customer Perform code reviews as per standards and provide timely status update Monitor and track defects and manage any change requests Participate in quality reviews and implement quality norms Build reusable components and participate in review processes Develop and review project consolidated status reports Perform all activities related to maintaining successful knowledge management, including re usage, accuracy and efficiency Promote team work, motivate, mentor and develop subordinates Provide application production support as per process/RACI (Responsible, Accountable, Consulted and Informed) Matrix

We have immediate requirement on SAP UX - UI5 Development contract to HIRE for client for HCL . Job Details Skills SAP UX - UI5 Development Experience 5+ Years LocationPan India Job type Contract Payroll company Interested candidates share the profile with below details at Current CTC : Expected CTC Notice Period SAP UX - UI5 Development Proficient in Fiori /UI5 development Good to have prior BTP experience, CAPM knowledge minimum exp is 5 years. At least 2 full lifecycle implementations. Good to have Nodejs Location - Bengaluru,Chandigarh,Dadra & Nagar Haveli,Daman,Diu,Goa,Haveli,Jammu,Lakshadweep,Nagar,New Delhi,Puducherry,Sikkim

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Systems Test Engineering General Summary Automation Scripting Knowledge of Automation Scripts is mandatory – Python / Perl / TCL Traffic Analyzers Wireshark, Ethereal, airopeak/omnipeak Technologies with sound knowledge GPON/XGS-PON/L2/L3 network protocol Test experience with minimum of 1 to 5 years WLAN Testing (added advantage) Independent Project handling with analytical ability Testing Experience Functional and Performance Experience in Broadband technologies (GPON,XGS-PON,OLT, ONT) L2/L3 network protocol Have worked on testing of ONT/OLT products. Protocols/Layers with good theoretical & practical knowledge Sound knowledge on L2/L3 network protocol : TCP/IP, NAT,IGMP, QOS, DHCP, VLAN, PPPoE, PON: GEM Frame, T-CONT,GEM Ports, QoS, GPON, XGSPON WLAN: Basic Knowledge on WLAN Traffic Generators Understating and Usage of Traffic generator tools like OLT / ONU / Spirent / Ixia / Chariot/ Veriwave. Knowledge on RFC2544, RFC2889, RFC3918 tests etc. Operating Systems Windows 10/XP/Win7, Linux Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Test Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Test Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. Qualification : Bachelor of engineering. E&C preferred. Skills / Attributes Require Should possess strong knowledge in GPON/networking/WLAN and manual testing of networking products Must have good experience in testing ONT/OLT Products Must have good experience in testing of layer-2 to layer 7 protocols Posses high Debugging capability Must be capable of analyzing new feature, creating test plans, and adding new test cases Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3077123

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required ToolsCadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

As an Applied R&D Engineer in the Integration, Verification & Testing (IVT) team, youll play a vital role in shaping next-gen telecom solutions. Youll be responsible for end-to-end testing of 4G and 5G Packet Core Call Processing, including test case preparation, execution, and automation. Your day-to-day will involve integrating software and hardware components into platforms or system releases and verifying them against defined requirements. Youll contribute to specification reviews, ensuring that all scenarios are thoroughly evaluated from the start. With a strong focus on quality, youll identify, isolate, and resolve issues while applying your expertise to determine root causes effectively. Your work will also include setting up and maintaining lab environments, tools, and devices to support seamless testing operations. You have: B.E/B.Tech/M.E/M.Tech degree in Computer Science, Electronics, Electrical, Information Science, or Telecom or equivalent with 28 years of experience in the Telecom Testing domain. Hands-on experience with 4G/5G core networks, particularly MME and AMF. Strong scripting skills in Tcl/TK, Perl, awk, sed, Python, TTCN-3, or other scripting/automation environments. Solid understanding of telecom protocols, including 4G ( NAS, S1AP, GTP, DIAMETER) / 5G ( HTTP2, SBI). Proficient in using tracing tools like WireShark and protocol analyzers such as Spirent. Good to have: Experience in delivering Software as a Service (SaaS) over any cloud platform. Familiarity with OpenStack and Nokia CloudBand Application Manager and Infrastructure Software Demonstrates strong teamwork, self-motivation, and a high level of commitment to excellence. Brings experience in testing telecom/IP-based products with solid understanding of SDLC and Agile testing methodologies. Skilled in functional, non-functional, performance testing, and test automation, with the ability to quickly grasp complex systems and become an expert in key areas. Stays updated on evolving cloud infrastructure and contributes effectively in a global, cross-functional team involving developers, product managers, and support teams across geographies. Thinks creatively to simulate complex real-world scenarios and supports the development and implementation of automation strategies for features of varying scale. Possesses strong problem-solving skills, clear communication, attention to detail, and a customer-centric mindset while collaborating in a diverse, multicultural environment.

Skill: SAP MM+S4 HANA Notice Period: Immediate Joiners Employee type : C2H Job Description: Must have Experience on SAP MM+S4 HANA Need to have good Communications skills

Skill: AEM Notice Period: Immediate Joiners Job Description: Must have experience on AEM Need to have good communication skills

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Lead Engineer Location: Mysore Work Type: Onsite Job Type: Full time Job Description: Strong proficiency in Verilog and SystemVerilog, with experience in designing finite state machines (FSMs), clocking, reset strategies, and bus architectures. Capable of developing microarchitecture from specification to RTL, including block and subsystem design, as well as thorough documentation. Skilled in RTL debugging, with working knowledge of synthesis processes and timing closure. Familiar with industry protocols and integration, such as AXI, APB, AHB, PCIe, SoC integration, design-for-test (DFT), and power domain management. Good to Have Skills: Experience with scripting and automation using Python, Tcl, or Perl to streamline design flows. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, AMS integration, UPF-based low-power design, post-silicon debugging, and a proactive approach to automation TekWissen® Group is an equal opportunity employer supporting workforce diversity.

Working with key accounts and business line COEs in stitching together storylines, Presales and solutions to address client requirements leveraging specific portfolio offers and solutions from AMS, Cloud, SAP, Data, Applications Modernization etc Working with accounts and business lines in stitching together value stories, best in class solutions, sales pitches and differentiating assets to address client requirements leveraging specific portfolio offers and solutions of Capgemini - Preparing strategic solution pitches for identified opportunities and supporting account teams in presenting them to clients in workshops Results Expected: Making a measurable impact on the pipeline of strategic opportunities for the business unit and conversions. KPIs will be around opportunities won. Skills and experience required for the role - Experience in creating impactful value stories for clients in various portfolio and solution domains - Experience in working on deals supporting proposals and working with cross service line teams/practices for driving value proposition This role is relevant to people who want to learn about Capgemini solutions and value propositions and in the future step into account manager or solution leader roles.

To perform activities associated with one or more software engineering lifecycle phases Principal Accountabilities: Understand customer requirements and suggest solutions or alternatives Fill timesheets and complete invoicing process on or before the deadline Engage with customer teams on an ongoing basis on all aspects of project delivery Seek informal feedback and escalate any issues to seniors in the team Develop software code as per specifications, by understanding customer requirements Track open tickets/ incidents in queue and allocate tickets to resources Constantly review if there is a better way of doing things, which may help with economising time or money or deliver better to the customer Perform code reviews as per standards and provide timely status update Monitor and track defects and manage any change requests Participate in quality reviews and implement quality norms Build reusable components and participate in review processes Develop and review project consolidated status reports Perform all activities related to maintaining successful knowledge management, including re usage, accuracy and efficiency Promote team work, motivate, mentor and develop subordinates Provide application production support as per process/RACI (Responsible, Accountable, Consulted and Informed) Matrix

Job Requirements We are looking for the engineers with 7+ years of experience in the Physical Design Domain. This is a on-site contract role based in Hyderabad. Job Description: Engineer should be able to guide the team(sub-lead or lead based on experience), analyse/document the issues/give fixes and track the milestones. One should have the basic experience in analyzing the calibre reports too. Work Experience Qualifications: 1) 7+ years of experience as a Physical Design Engineer. 2) Bachelor's or Masters degree in the related field. 3) Good at the basics of Digital Electronics. 4) Implementation, STA and Physical Verification skills. 5) Experience in tapeout using the implementation tools: icc2/fusion Compiler, signoff tools: PT. 6) Strong analytical and problem solving skills. 7) Excellent communication skills. 8) Able to write scripts using TCL/Python/PERL. 9) Experience in leading the team/capability to lead a team.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Board bring-up activities for Software components like bootloader, platform managers, Linux Kernel, Linux drivers, Baremetal drivers and applications for ARM based boards. Testing, Verification bring up of Linux Kernel and Linux Drivers I2C, Flashes, USB , Ethernet, PCIe , DDR memory Tests etc. Develops and executes test plans to evaluate functionality, security, and efficiency of firmware utilizing emulation and evaluation boards for pre-silicon and post silicon verification. Analyzes, tracks, and debugs testing failures to determine corrective measures. Collaborates directly with the development team to assess test plan requirements and resolve failures. Run the Regression tests, triage issues, create Defects in the system and work with development team for closure. Automate and the functional and System level tests using Python and integrate the same in Test Automation framework and maintain the Test artifacts for any updates in the Test cases or in Test framework Skills Must have Candidate should have 4-7yrs experience Working experience in verification and testing of Linux based Embedded System software etc. Good experience in Linux Device Driver Verification and validation on Linux, Bare metal, Real Time Operating Systems. Skills in compiling/building/cross-compiling, debugging, testing, deploying Bootloader, TF-A, Linux Kernel, Device tree, Middleware software, and BareMetal application images for board bring up activities through JTAG debuggers & Emulators using different boot modes Good understanding of any one of SoC/Processing Technologies like ARM/RISC-V/X86, MMU, Interrupt handling, Caches etc. Hands on with one or more peripherals/controllers like UART, I2C, SPI, USB, SD, eMMC, QSPI, PCIe etc. Define, Design and Develop manual/Automation test cases for Embedded system projects Programming skills in C/C++, Makefile, Linker file creation, scripting language Python/Shell/Tcl Experience in GIT environment and Test Automation framework Pytest, Jenkins etc. Good to have exposure in design tools like VIVADO, VITIS, Configuration management tools like GIT/Perforce, JIRA, Confluence etc. Nice to have Education Requirements: B.E/B.Tech or M.E/M.Tech in Electronics & Communications or Computer Science Other Languages English: B2 Upper Intermediate Seniority Regular Hyderabad, IN, India Req. VR-115375 Manual Testing Automotive Industry 26/06/2025 Req. VR-115375