Sr. Backend Integration Engineer

Silicon Image India Research Development

9 - 14 years

4 - 8 Lacs

pune

Posted:-1 days ago| Platform:

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Skills Required

c++ physical design soc digital design vhdl scripting verilog hdl rtl design fpga rtl coding perl system verilog electronics engineering asic sta python asic verification vlsi design c rtl uvm verilog asic design fpga design integration vlsi

Work Mode

Work from Office

Job Type

Full Time

Job Description

This is a full-time individual contributor position located in Pune, India.
The qualified candidate will be implementing RTL to GDSII flow for complex design.
The qualified candidate will lead and work on full chip backend integration and physical design including power and bump planning
The qualified candidate will drive all physical signoff checks including DRC, LVS, PERC, ESD and any other signoff checks for seamless tapeout activities
The qualified candidate is expected to drive power and bump planning and support package tapeout activities
The qualified candidate is expected to have some scripting knowledge or perl /python etc to improve design efficiency and methodology development.
Collaborate with cross functional teams on timing , power and design optimization
The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.

Accountabilities:

Serve as a key contributor to FPGA design efforts.
Drive full chip integration and physical verification activities and bring best-in-class methodologies to achieve best power, performance, and area.
Ensuring design quality through all physical design quality checks and signoff.
Develop strong relationships with worldwide teams.
Mentor and develop strong partners and colleagues.
Occasional travel as needed.

Required Skills:

BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
9+ years of experience in driving backend integration activities of ASIC blocks and full chip.
Experience on working with industry standard physical design tools including Innovus, Calibre, Virtuso, voltus, calibre, Tempus, conformal etc.
Independent worker with demonstrated problem-solving abilities.
Proven ability to work with multiple groups across different sites and time zones

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