131 Signal Integrity Jobs - Page 4

The focus of this role is in developing clocking strategies that meet stringent timing, power, and area constraints while managing clock distribution across the SoC. THE PERSON: As the SoC Clock Design Lead, you will be responsible for the architecture, design, and optimization of clocking structures within complex SoCs. This position involves working closely with cross-functional teams, including RTL, physical design, power, and timing engineers, to ensure efficient and high-performance clock networks. KEY RESPONSIBILITIES: Proficiency in clock tree synthesis (CTS) and clock network optimization using tools like Synopsys FC, ICC2. Strong experience in static timing analysis (STA), clock domain crossing (CDC) checks, and jitter/skew analysis. In-depth knowledge of clock gating, power optimization, and low-power design techniques. Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancements Familiarity with advanced technology nodes (5nm and below) and their specific challenges in clock design Understanding of signal integrity, electromigration, and power integrity in the context of clock networks. PREFERRED EXPERIENCE: Define and implement the clock architecture and distribution strategy for SoCs, optimizing for performance, area, and power requirements. Lead clock tree synthesis, insertion, and optimization to achieve timing closure and reduce clock skew/jitter across the SoC. Implement and validate clock gating techniques to minimize dynamic power consumption and enhance SoC energy efficiency Work with RTL, timing, power, and PD teams to resolve clock-related issues, optimize clock distribution, and ensure alignment with SoC design goals Create and maintain custom scripts in Perl, Python, or Tcl to automate clocking tasks, streamline workflows, and improve productivity ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering.

PCB design principles, Software Expertise in Altium Designer for schematic capture, PCB layout, & library management High-speed PCB design Power electronics, SI/PI concepts, & EMI/EMC compliance DFM, DFA, & PCB manufacturing processes IPC standards Required Candidate profile Experience in PCB design, preferably with high-speed and/or complex multilayer boards Effective communication skills Knowledge of Flex PCB and HDI PCB design

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Overview As a leading global aerospace company, Boeing develops, manufactures and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven culture At Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring together different perspectives and thoughts – enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing. Position Overview The Boeing Company is looking for a Lead - Hardware (Integrated Project Team) IPT Engineer, for Electronics Product team located at Bangalore, India .Boeing India Engineering oversees the design, development, manufacture, integration and testing of LRU design and analysis for various Avionics systems. Position Responsibilities: The successful candidate will perform the following duties: You will be responsible for the development of electronics hardware for avionics application in close co-ordination with software, firmware, mechanical and certification authorities. You will engage into planning, tracing performance to planned progress against technical TPMs for hardware designs from a team upon packaged solutions that would contain processors, Input Output interfaces, electromechanical packaging, EMI/EMC Solutions, Analog and digital electronics, power supplies and other custom electronics designs. You will work with other concurrent engineering teams such as software and certification authorities to prove compliance upon developed hardware through traceability and related tools. Manages small to medium projects with minimal mentorship from Program Group Leads project reviews with Larger Program Teams through events such as PDR, CDR and TRR Lead technical scope development through robust traceable compliance metrics and standards Responsible for developed Project Plan, schedule, resource plan and project budget within the project team Responsible to understand and report the project technical plan to progress against TPMs decided Responsible to work with leads and members to identify risks and plan execution of hardware projects with clear understanding upon stakeholder givers and takers Responsible for supervising engineering achievements like on time delivery, quality etc. Responsible to seamlessly guide a technical team towards scope and resolving intra functional and inter functional conflicts for unified project team goals Responsible to co-ordinate with supply chain/sourcing and regulatory authorities for hardware development globally Responsible to deploy risk management techniques to avoid/mitigate project risks Basic Qualifications (Required Skills/Experience) Bachelor’s Degree or higher is required. Has worked on multiple hardware project lifecycles Lead hardware development over Galley products Lead hardware teams for Avionics high design assurance complete product development Hands on Experience upon embedded hardware platform, its concurrent engineering with software and systems team Strong hardware design practices, with a focus on safety and reliability Hands on experience upon Analog, Digital and Mixed signal circuit design, development and testing is a MUST Ability to understand detailed design analysis against worst case variations and comprehensively prove performance of designs to requirements. Comprehensively built upon sub-tired requirement compliance to larger system level requirement compliances Preferred Qualifications (Desired Skills/Experience) PMP Certification and/or Agile Certifications Typical Education & Experience: Typically, 13 to 16 years' related work experience. Advanced degree (e.g. Bachelor, Master, etc.) preferred. Relocation This position offers relocation based on candidate eligibility within INDIA . Applications for this position will be accepted until Jun. 06, 2025 Export Control This is not an Export Control position. Education Bachelor's Degree or Equivalent Required Relocation This position offers relocation based on candidate eligibility. Visa Sponsorship Employer will not sponsor applicants for employment visa status. Shift Not a Shift Worker (India) Equal Opportunity Employer: We have teams in more than 65 countries, and each person plays a role in helping us become one of the world’s most innovative, diverse and inclusive companies. We are proud members of the Valuable 500 and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited toconducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews.

Major skills that we need to look for -> Hardware Design, Board design, Digital circuit design, Low power design, Board debug, Board testing, x86, Documentation Detailed JD :- Hardware design engineer with x86 Board design background. Strong fundamentals and experience in Digital circuit design and low power Electronic circuits. Understanding of signal integrity, EMI/EMC concepts for Digital and Power Electronics Experience in at least one complete project starting from the high-level design to the final validation. Should be able to independently handle the schematic design, design analysis and review coordination with peer designers, Layout, SI and EMC teams. Experience in board bring-up and issue investigation & triage, in coordination with firmware and software teams. Experience in preparing and reviewing hardware design documentation and issue investigation reports. Should be able to develop the board bring-up plan, be able to identify the test equipment required and execute independently . Strong communication and interpersonal skills to collaboratively work with various cross functional teams involving post silicon IP Validation, BIOS and Driver Development/QA.

Job Description Introduction: Digital Transformation Solutions (DTS) . Extensive experience in defining, developing, and implementing security software, ideally with a strong embedded firmware development background About the Role Bangalore Responsibilities: Extensive experience in STA with deep understanding of technologies, trends and needs Extensive experience in defining, developing, and implementing security software, ideally with a strong embedded firmware development background Ability to troubleshoot complex issues and debug firmware What You Need Bachelor s or Master s degree in Electronics Engineering, Computer Engineering, or related field with 10 years or more relevant experience. Static Timing Analysis Engineer - Job description : (6 + Yrs Exp) STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Hands-on experience with STA tools - Tempus In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling What is Nice to Have Strong collaboration skills to work directly with customers and across multidisciplinary teams, including silicon, software, firmware, board design engineers and program management. Experience in Automotive software development processes. Furthermore, you are: Innovator finding break-through solutions for complex automotive problems Driving for continuous improvements. What Makes You Eligible Any offer of employment is conditioned upon the successful completion of a background investigation and drug screen. Dedicated performer & team player with the ability to advocate appropriately for product quality. Relentless learner with a dedication to learn new technologies and test methods Self-driven and Innovative to drive continuous improvements in Test process Resourcefulness in triaging problems and coordinating with multiple teams for issue resolution Strong written, verbal communication and inter personal relationship skills What We Offer Flexible work environment, allowing for full-time remote work globally for positions that can be performed outside a HARMAN or customer location Access to employee discounts on world-class Harman and Samsung products (JBL, HARMAN Kardon, AKG, etc.) Extensive training opportunities through our own HARMAN University Competitive wellness benefits Tuition reimbursement Be Brilliant employee recognition and rewards program An inclusive and diverse work environment that fosters and encourages professional and personal development You Belong Here . About HARMAN: Where Innovation Unleashes Next-Level Technology . . If you re ready to innovate and do work that makes a lasting impact, join our talent community today !

Design multilayer PCBs using cadence allegro tools Collaborate with electrical engineers to translate schematics into PCB layouts Define board stack-ups, impedance control, and layout constraints Perform signal integrity, power integrity, and DFA/DFT/DFM analysis Generate and review fabrication and assembly documentation (Gerber files, BOMs, pick & place, assembly drawings) Work with vendors and manufacturers for PCB fabrication and assembly Create and maintain PCB design libraries Ensure compliance with regulatory standards (e.g., IPC, RoHS, UL) Proficiency with one or more PCB CAD tools Understanding of high-speed design principles and layout best practices Familiarity with EMI/EMC considerations and thermal management Strong attention to detail and analytical skills Experience with HDI, mixed, and RF PCB designs Knowledge of IPC standards (e.g., IPC-2221, IPC-7351) Experience with DFx

Design, simulate, test, and debug analog/digital/RF circuits Create schematics Work closely with PCB layout engineers and manage design flow Selection of components, create & optimize BOM Perform hardware testing & debugging Use Oscilloscope, Logic Analyzer, Multimeter, Function Generator Ensure RoHS, IEC, ISO, EMI/EMC compliance Perform thermal and signal integrity analysis

Video Editing Intern Jaipur (In-office) - Digi Spheres Video Editing Intern Jaipur (In-office) Job Summary: We re seeking a creative and technically skilled Video Editing Intern to bring our content to life. You ll be responsible for editing short-form and long-form content for various platforms. Key Responsibilities: Edit videos, reels, and motion graphics for client campaigns Add music, text, transitions, and other visual effects Optimize content for Instagram, YouTube, and other platforms Collaborate with content creators and strategists for ideation Requirements: Proficiency in Premiere Pro, Final Cut Pro, or CapCut Strong sense of pace, timing, and narrative flow

Expertise in Electrical Bench Characterization Expertise in Electrical performance validation: PCIe Gen5, LP / DDR4 / 5, Ethernet (10G/25G) Expertise in BERTs, VNAs, Oscilloscopes, Signal Integrity Expertise in debugging silicon / platform issue Expertise in data analysis / statistics Expertise in Test scripting (LabVIEW / Python preferred) Expertise in test automation Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit.

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphics. Conduct DRC/LVS checks and ensure design compliance with specifications. Support the verification team in physical design verification activities. Participate in design reviews and provide feedback for design improvements. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2-7 years of experience in ASIC physical design or related roles. Strong knowledge of ASIC design flow and methodologies. Proficiency in using EDA tools for physical design (e.g., Cadence, Synopsys, Mentor Graphics). Experience with place and route, timing closure, DRC/LVS checks, and physical verification. Familiarity with scripting languages (e.g., Perl, Tcl, Python) for automation of design tasks. Understanding of semiconductor manufacturing processes and design for manufacturability (DFM). Strong problem-solving skills and attention to detail.

We are looking for a PCB (Printed Circuit Board) Design Engineer for designing and developing layouts for circuit boards used in electronic devices. They need to work closely with hardware engineers to translate electrical schematics into manufacturable PCB designs using CAD tools like Altium Designer, Eagle, or OrCAD. The role involves component placement, routing, signal integrity analysis, and ensuring design for manufacturability (DFM). Attention to detail, knowledge of industry standards, and the ability to troubleshoot and optimize designs are key to success in this role. Key Responsibilities: Schematic entry Component footprint/library creation Designing of High Speed PCBs to meet maximum performance Releasing of Gerber, BOM and documentation files Help resolve technical queries from PCB fabricators and contract manufacturers. Key Skills & Competencies: Knowledge of industry standards Knowledge of IPC-2221/2222/7351 Familiarity with different PCB CAD tools like PADS PCB, Allegro, Altium. Expedition, Board Station, CADStar, Protel (Optional Value added) Strong background with through hole, SMT, and BGA technologies using dual-sided assemblies, and multilayer boards Good understanding of PCB stack up requirements to finalize the same based on design complexity and design requirements Knowledge in Power supply layout [Switch mode, high power etc. Well versed in blind, buried laser micro via and technologies Experience in high speed bus routing, differential pairs and impedance control routing to meet signal integrity Should be able to work independently and deliver the work assignments. Good expertise in DFM, DFA and DFT Knowledge of various PCB design guidelines Good understanding of PCB manufacturing process and requirements Personal Attributes: High attention to detail and quality orientation. Strong organizational and time-management skills. Good communication skills to report issues and collaborate effectively.

JD Highlights: 6 to 10 years of relevant experience Electrical performance: PCIe Gen5, LP/DDR4/5, Ethernet Tools: BERTs, VNAs, Oscilloscopes Signal Integrity basics, hands-on debug Test scripting and automation (LabVIEW/Python preferred) Cross-functional collaboration

Job Description Role: Senior Manager, IO Design Memory Technology Competencies: Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Extensive Hands-on design experience in IO Design(LVCMOS, HVCMOS, DDR, LVDS) 15+ years of Experience on handling IO designs, projects working with BU, Stake holders NAND Flash Design knowledge is plus Expertise in ESD, Powerbus, Floor plan, Layout guidelines Expertise, knowledge of advanced DDR algorithms : Training modes and DFE/CTLE/Compensation Techniques, Clock skew techniques Management and Lead experience to handle Team of IO engineers Experience in working with cross geo, cross team functions and stake holder management Expertise with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: finesim, hspice & other flows Good to have: Lead team of experienced IO Design Engineers Strategic development of next generation IO for scaling speed Build Best in Class IP Design Handling BU communication on all IO Roadmap, RMA, FA Drive E/E IO Design capability and execution till Silicon to Productization Qualifications B.TECH/M.TECH in Electrical / Electronics / VLSI / Microelectronics with 15+ years of experience

High speed VLSI/SBC/Analog/Digital/RF circuit design according to design rules. Design of product/card schematics. Preparation of related hardware design documents, document review. Leading or assisting through board bring up, helping resolve hardware issues. Review of PCB layout, BOM and other hardware documents. Engaging with in-house or third-party lab for product qualification as per teststandards. Required Skills: Knowledge of Orcad / Altium, Protel or other design tools. Well versed with EMC design techniques and signal integrity issues. Experience with hi-speed processor board/sbc design, aware of clock stability issues having worked with high speed RAM/Flash/PHY and other peripherals. Well versed with EMC design techniques and signal integrity issues. Min. 3 years hands-on in hardware development cycle, hardware debugging, natural ability to solve hardware problems. Experience in EMC testing, having successfully worked on product qualification for CE or IEC or MIL 461E test standards RequiredQualification and Experience: BE/B. Tech/M. Tech in Electronics / ETC / Instrumentation. Apply Now

1. Candidate shall have experience in handling multiple end to end product project around RF design, analysis, testing, calibration, regulatory compliances and release of products for commercial deployments 2. Relevant experience of 3+ years in RF Design. Responsibilities 1. Lead the design, simulation, and verification of complex analog and mixed-signal circuits, Signal integrity, power integrity, impedance Analysis. 2. Perform advanced simulations and analyses to ensure exceptional circuit performance and compliance with specifications. 3. Create comprehensive documentation of design methodologies, specifications, and outcomes. 4. Multi radio front end and radio optimisation. 5. Extensive knowledge on RF matching, filter design and antenna matching. 6. Conversant with lab equipment like Spectrum Analyzer, Network analyser, RF Signal generators , IQXEL, MT8852 etc. 7. Experience on EMI/EMC, Antenna design, Signal Integrity and Thermal Analysis will be a key skill. 8. Design and develop Regulatory certified BLE, ZigBee, Wi-Fi modules. 9. Work closely with cross functional teams to derive the design specification for Modules. 10. Prototype Board bring-up, Validation and Characterization. 11. Handover design to manufacturing and help to derive the production test plan. 12. Documentation of design, test plan and test results. 13. Supporting Customer support team in debugging critical customer issues. 14. Radio side design and debugging. 15. RF performance evaluation, calibration and optimisation. 16. Link budget and harmonics analysis. 17. Tuning and optimisation of RF front end. 18. Deep understanding on radio chip, physical layer customisations and its impacts on the radio performance. 19. Understanding of various physical layer standards. 20. Willingness to contribute in global standards committee of next generation wireless systems. 21. Ownership of product level EMI/EMC compliances for global requirements as well. 22. Schematic, Layout and BOM selection. Mandatory Key Skills MT8852,Signal integrity,power integrity,debugging,Spectrum Analyzer*,Network analyzer*,RF Signal generators*,IQXEL*,RF design*

Pcb design engineer Mysore location Minimum of 10 years of experience in PCB design and schematic capture with expertise in Altium Designer. Strong understanding of Analog and Digital circuit design. Experience in high-speed PCB routing and signal integrity analysis. Knowledge of EMI/EMC guidelines for PCB design. Familiarity with IEC 60601-1 and IEC 60601-1-2 standards Experience with cable assembly drawings in Altium designer. Ability to interact with PCB/PCBA manufacturers and suppliers to resolve technical issues. Knowledge of DFM (Design for Manufacturability), DFT (Design for Testability), and DFA (Design for Assembly) principles. Knowledge of thermal management techniques in PCB design Strong analytical, troubleshooting, and problem-solving skills. Excellent communication and teamwork skills.

Roles and Responsibility PD: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) Well versed with the timing closure (STA), timing closure methodologies Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification Experience in lower tech node ( Good automation skills in PERL, TCL and EDA tool-specific scripting Able to take complete ownership for Block/sub-system for complete execution cycle Out of box thinking to meet tighter PPA requirements Qualification: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Experience - 11+

Understand and align the team's contributions with project goals, recognizing their impact within the project management framework Operate within financial and program constraints while considering budgetary implications in design options Develops construction cost estimates and estimates of technical efforts/ fee proposal for projects Work within the financial and programme constraints and consider financial implications in producing design options Performs quality control review of design documentation, calculations and drawing Lead EMI and E&B activities, offering guidance, support, and performance management Participates in development of technical proposals. Provides input to the development of engineering budget and schedule to meet requirements. Qualifications Master of Engineering degree (or equivalent education) in an appropriate engineering discipline from an accredited college or university. Chartered Engineer (CEng), or Professional Engineer (PE) license or equivalent in the relevant field from any global organization (e.g., Institution of Civil Engineers, UK) 12+ Years of experience Contribute to design development, design risk and mitigation, and value engineering with a focus on electromagnetic compatibility (EMC) and electromagnetic interference (EMI) Provide expert technical guidance and ensure adherence to earthing and bonding (E&B) standards throughout the design process Present EMC/EMI and E&B strategies effectively to stakeholders and non-technical leads Develop and deliver Earthing (Grounding) and Bonding Control Strategy reports Produce detailed design documentation, including calculations, design sketches, and technical specifications Participate in interdisciplinary design team meetings and coordinate with sub-consultants and equipment suppliers for accurate design information Review and verify design drawings and ensure they align with project requirements and standards Prepare technical reports and assess project specifications for construction compliance Provide input to E&B strategy and conduct power quality compatibility assessments Working with design engineers to advise on EMC test specifications and production of test procedures and reports as required Advise appropriate EMC solutions through design analysis to identify required control techniques and good design practice Earthing (Grounding) & Bonding Design: Produce comprehensive reports detailing solutions for each facility Produce calculation reports to justify results and ensure compliance with required values. Develop and mark up drawings, including grounding grid layouts, cross-sections, riser diagrams, and bonding drawings. Technical specifications of the elements Lightning Protection Design: Produce reports outlining solutions for each facility. Create calculation reports to validate results and meet compliance requirements Develop and Mark up drawings for lightning protection layouts and connections to main grounding grids. Define technical specifications for lightning protection elements. Ensure that technical and safety standards are maintained across all design activities tin order that successful project implementation and future reliability is achieved. Carry out risk assessments and provision of design information for Health and Safety file. Additional Information AECOM provides a wide array of compensation and benefits programs to meet the diverse needs of our employees and their families. We also provide a robust global well-being program. Were the worlds trusted global infrastructure firm, and were in this together your growth and success are ours too. As an Equal Opportunity Employer, we believe in each persons potential, and well help you reach yours. #LI-FS1 About AECOM AECOM is proud to offer comprehensive benefits to meet the diverse needs of our employees. Depending on your employment status, AECOM benefits may include medical, dental, vision, life, AD&D, disability benefits, paid time off, leaves of absences, voluntary benefits, perks, flexible work options,well-being resources, employee assistance program, business travel insurance, service recognition awards, retirement savings plan, and employee stock purchase plan. AECOM is the global infrastructure leader, committed to delivering a better world. As a trusted professional services firm powered by deep technical abilities, we solve our clients complex challenges in water, environment, energy, transportation and buildings. Our teams partner with public- and private-sector clients to create innovative, sustainable and resilient solutions throughout the project lifecycle from advisory, planning, design and engineering to program and construction management. AECOM is a Fortune 500 firm that had revenue of $16.1 billion in fiscal year 2024. Learn more at aecom.com. What makes AECOM a great place to work You will be part of a global team that champions your growth and career ambitions. Work on groundbreaking projects - both in your local community and on a global scale - that are transforming our industry and shaping the future. With cutting-edge technology and a network of experts, youll have the resources to make a real impact. Our award-winning training and development programs are designed to expand your technical expertise and leadership skills, helping you build the career youve always envisioned. Here, youll find a welcoming workplace built on respect, collaboration and community - where you have the freedom to grow in a world of opportunity. As an Equal Opportunity Employer, we believe in your potential and are here to help you achieve it.

Knowledge of High-Speed Board Design Experience in designing with memories like DDR3 / DDR4 / eMMC / NAND / NOR Flash etc. Experience in designing with High-speed communication protocols like PCIe / SerDes / USB3.0 / SGMII / SFP+ /10G/100G/ Hands-on experience with MII, SGMII, RGMII, HSGMII, QSGMII, XGMII and its PHY interfaces Hands-on experience with Intel or Broadcom or Marvel or MediaTek Quad/Octal port Ethernet PHYs transceivers Should have design experience in Multiport Gigabit Network Switches, Hubs and Gigabit Router Added Advantage for knowledge of PoE 802.3at , PoE+ 802.3bt Type 2 , or PoE++ 802.3bt Type 3 or 4PPoE PoE++ Type 4 Should Have Experience of different Gbit Standard such as 1000Base – SX, 1000Base-LX, 1000Base- CX, and 1000Base-T 1Gb/s SFP(INF-8074i),10Gb/s SFP+ (SFF-8431 4.1) or 25Gb/s SFP28 (SFF-8402) and QSF,QSFP+,QSFP28 would be advantage Experience with High-speed Hardware design, Complex Analog and Digital Hardware System level design, circuit analysis, SI/PI, PSPICE simulation, Boundary scan, EMC/EMI analysis and safety standards Responsibilities include Schematic Capture, Component Selection, Library Creation and Guiding Board Layout. Should Have product development understanding like Enterprise switching, Port extender, Embedded Ethernet fabric, and TSN products Hands-on experience in Telecom/Datacom product design Experience like PDH/SDH/SONET/ and fibre optic products Should Have telecom backhaul Network transmission products design Experience, Experience in working with complex ASSPs, Microprocessors/controllers and FPGAs Experience in Signal Integrity / Power Integrity Should have worked on testing equipment like high-speed Oscilloscope, Network analysers, spectrum analysers etc

Role & responsibilities High-Speed PCB Design: Develop PCB layouts for high-speed systems, including DDR, PCIe, USB, Ethernet, and other high-frequency interfaces. Signal and Power Integrity: Perform signal and power integrity analysis to ensure optimal design performance. Layer Stack-up Design: Define PCB stack-ups and impedance-controlled designs for high-speed and high-density applications. Simulation and Validation: Use simulation tools to validate designs for crosstalk, impedance matching, and high-speed signals. Component Placement and Routing: Optimize placement and routing strategies to meet performance, manufacturability, and cost requirements. Design for Manufacturing (DFM) and Test (DFT): Collaborate with fabrication and assembly teams to ensure manufacturability and testability of designs. Documentation: Generate detailed design files, BOMs, and fabrication documentation. Compliance: Ensure designs adhere to industry standards (e.g., IPC-6012, ISO 9001) and regulatory requirements. Collaboration: Work closely with hardware, firmware, and system engineering teams to meet project requirements. Preferred candidate profile Bachelors degree in Electrical Engineering, Electronics, or a related field. 3+ years of experience in PCB design with a focus on high-speed digital and RF designs. Expertise in Altium for PCB Design Strong knowledge of signal integrity, power integrity, and EMI/EMC design principles. Proficiency in high-speed interfaces (DDR3/DDR4/DDR5, PCIe, SerDes, etc.). Familiarity with simulation tools like HyperLynx, Ansys, or SIwave for signal and power integrity analysis. Hands-on experience with impedance-controlled designs and differential pair routing. Solid understanding of PCB fabrication and assembly processes.

locationsIndia, Bangalore time typeFull time posted onPosted 5 Days Ago job requisition idJR0274956 Job Details: About The Role : Foundry Services (FS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the best of Intel technologies to FS customers, differentiating and accelerating their solutions from architecture to post-silicon validation. We are looking experienced Floorplan Engineer to work on Foor plan, die estimation, Power planning of high performance designs . Responsibilities include Establishes the integration plans for die with optimization for package and board constraints. Bump planning, Die file generation , closing loop with package team on signal and power bump placement restrictions Create physical database for the IP or SoC. Collaborate with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio. Collaborate with the design teams on clocking and dataflow to deliver the physical block level floorplans for APR. Derive specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Coordinate with power delivery team on trade-offs for metal allocation for signal and power. Have excellent understanding on, die-per-reticle/good-die-per-wafer maximization, and right technology selection on metal layers usage maximization Good knowledge on RDL routing and efficient usage higher metal layers Performs integration of all dies in a package and completes the relevant checks before tape-out. Qualifications: Qualification : 12+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field. Must have led multiple SOCs in capacity of SOC Floorplan lead. Strong Expertise in Design planning, die estimation, Good understanding on package and board level requirement . Must have knowledge on clocking , high speed design signal routing, industry standard protocols and IP architecture; Good understanding on relevant areas of Library / Memory / technology/submicron issues . Teamwork / flexibility / ability to thrive in a dynamic environment are very important Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

In This Role, Your Responsibilities Will Be: Take ownership of the hardware development tasks and deliver without supervision while using their discretion to seek help when necessary. Develop design concepts and select the right components to ensure the design meets agreed upon functionality, reliability and cost expectations. Develop circuit/board design, building prototypes, board bring-up and debugging, enhancement of various IO modules, Communication and CPU cards used in Remote Automation business. Collaborate with multi-functional teams (component engineering, PCB layout, FPGA, software, testing, product management) to ensure overall system requirements are fulfilled with a cost-effective and high-quality approach. Support if any HW issues on the site as well as in manufacturing. Research on new technology trends and apply the opportunities to enhance product performance or to reduce cost. Support any hardware issues on the products reported from the field, as well as from manufacturing or compliance. Make technical presentations to peers and managers on the details of architecture, design, technical risks, etc. Use excellent communication skills to talk to technical architects on complex technical issues. WHO YOU ARE You can take Quick and decisive actions in fast-changing, unpredictable situations. You show a tremendous amount of initiative in tough situations; is exceptional at spotting and seizing opportunities. You can deliver messages in a clear, compelling, and concise manner and Adjust to the communication content/style to meet the needs of diverse stakeholders. You like to encourage the expression of diverse ideas and opinions. For This Role, You Will Need: Bachelors or above in Electrical Electronics Engineering or equivalent from an accredited college or university. Minimum 5 to 10 years of expertise in the field of Hardware engineering skills, along with the knowledge of agency/compliance requirements. Expertise in measurement and validation methods for hardware design and know-how to use the related instruments, to automate tests wherever necessary. Solid knowledge of electrical and electronics design and manufacturing. Knowledge of the fundamental theory of signal processing, circuit analysis, analog circuits design, and digital circuits design. Proficiency in the ECAD suite of tools, either from Mentor Graphics or Cadence or similar. Knowledge in Signal Integrity and simulations. Should be able to plan and coordinate tasks across multi-functional teams like Firmware, Mechanical, Component Engineering, PCB layout, etc. Should be able to take ownership of the complete electronics design life-cycle: from requirement to release for production. Preferred Qualifications that Set You Apart: Knowledge and experience in working with the hardware design as per IEC 61508 - functional safety. Hands-on experience in working on the failure analysis and estimation tools such as FMEDA, HAZOP, Fault Tree Analysis Our Culture Commitment to You . .

General Summary: As a global technology leader, Qualcomm is committed to pushing the boundaries of innovation. We are seeking a Senior Hardware Engineer specializing in Static Timing Analysis (STA) to join our world-class team. This role focuses on timing convergence for complex SoCs, IP blocks, and advanced technology nodes. The ideal candidate will have deep technical expertise in STA, strong problem-solving skills, and the ability to collaborate across design, physical implementation, and tool development teams. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 6+ years of relevant experience OR Master's degree and 5+ years of experience OR PhD and 4+ years of experience in Hardware Engineering or related fields Required Experience and Skills: 6+ years of hands-on experience in Static Timing Analysis (STA) for large ASIC/SoC designs Strong foundation in STA concepts including: Setup/Hold time analysis, Clock Skew, Latch Transparency Multi-cycle and zero-cycle path handling AOCV/POCV (Advanced/Parametric On-Chip Variation) Crosstalk, Noise Analysis, and Signal Integrity Hands-on experience with industry STA tools: Synopsys PrimeTime , Cadence Tempus Expertise in timing constraint management (SDC), including: Multi-voltage domains Multi-mode timing closure Domain crossings and feedthrough handling Familiar with full ASIC back-end design flows (RTL to GDS): Tools: ICC2 , Innovus , PT , Tempus Experience in SPICE simulations (Hspice/FineSim), Monte Carlo runs, and silicon-to-SPICE correlation Proficiency in scripting languages such as: TCL , Perl , Python , Awk Strong collaboration and communication skills; experience working in cross-functional teams Preferred Qualifications: Knowledge of Qualcomm Hexagon DSP IPs and their timing behavior Exposure to device physics and process technology enablement Familiarity with digital design flow and EDA automation Experience in timing methodology development and automation within STA/PD flows Previous experience in timing convergence for chip-level and hard macro-level designs Key Responsibilities: Own and drive timing convergence for advanced SoC and IP designs across PVT (Process, Voltage, Temperature) corners Perform STA signoff using industry-standard tools and methodologies Develop, maintain, and optimize timing analysis flows and scripts Work with physical design teams to define and validate constraints, analyze violations, and recommend fixes Support cross-functional teams in constraint development , clock tree synthesis , and timing closure Correlate SPICE simulations with STA results to ensure timing accuracy and model validity Lead timing reviews , debug issues, and document findings and methodologies Contribute to tool evaluations , timing methodology enhancements , and internal flow automation Level of Responsibility: Works independently and takes ownership of key deliverables Provides technical leadership and mentoring to junior engineers Influences project direction and STA methodology Communicates complex technical issues effectively to stakeholders

General Summary: Qualcomm is a global leader driving next-generation innovations in technology, pushing boundaries to enable smarter, connected experiences. As a Qualcomm Hardware Engineer in the DDR Physical Design (PD) team, you will be involved in planning, designing, optimizing, verifying, and testing advanced electronic systems including circuits, mechanical, Digital/Analog/RF/optical systems, test systems, FPGA, and DSP systems. You will collaborate closely with cross-functional teams to meet stringent performance and timing requirements for cutting-edge products. Positions & Experience Levels: Senior Lead: 6 to 8 years of experience (2 openings) Staff Engineer: 8 to 10 years of experience (1 opening) Senior Staff Engineer: 10 to 12 years of experience (1 opening) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field + 6+ years experience OR Master's degree + 5+ years experience OR PhD + 4+ years experience in Hardware Engineering or related field Key Technical Skills & Responsibilities: Static Timing Analysis (STA): Strong fundamentals in STA timing analysis, including AOCV/POCV concepts, CTS, timing constraints, latch transparency, 0-cycle and multi-cycle path handling Hands-on experience with STA tools like PrimeTime and Tempus Driving timing convergence at both Chip-level and Hard-Macro level STA setup, convergence, review, and sign-off for multi-mode, multi-voltage domain designs (including Qualcomm Hexagon DSP IPs) Signal Integrity and Parasitics: Deep understanding of cross-talk noise, signal integrity, layout parasitic extraction, and feed-through handling ASIC Back-end Design: Knowledge of back-end flows and tools such as ICC2, Innovus Experience with circuit simulations using Hspice, FineSim, and Monte Carlo methods Correlation between silicon and spice simulation models Scripting and Automation: Proficient in scripting languages: TCL, Perl, Awk Experience with automation scripting for STA and physical design tools Familiarity with design automation flows from RTL to GDS (using tools like ICC, Innovus, PrimeTime, Tempus) Process Technology: Basic device physical knowledge Familiarity with process technology enablement and related simulations Soft Skills: Strong technical writing and communication skills Willingness to work collaboratively in a cross-functional and global environment

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn