Pyshical Design Engineer

#Connections #Hiring

Hi Connections,

We are hiring....

Job Title: Physical Design Engineer (PD)

Location: Hyderabad / Bangalore

Department: Semiconductor / VLSI Physical Design

Employment Type: Full-Time

Experience: 3+Years

Job Summary:

We are seeking a skilled Physical Design Engineer to take ASIC/SoC designs from RTL to GDSII, ensuring optimal performance, power efficiency, and area utilization. The role involves synthesis, floorplanning, placement, routing, timing closure, and physical verification, working closely with RTL, verification, and DFT teams to achieve first-silicon success.

Key Responsibilities

● Perform RTL synthesis with timing, area, and power constraints.

● Develop floorplans considering macro placement, power grids, and clock tree planning.

● Execute placement, clock tree synthesis (CTS), routing, and post-route optimization.

● Drive timing closure across multiple process, voltage, and temperature (PVT) corners.

● Implement low-power techniques such as clock gating, multi-Vt, and power gating.

● Perform power analysis and signal integrity checks.

● Run physical verification (DRC/LVS) to ensure manufacturability.

● Work with foundries for process-specific requirements and design sign-off.

● Collaborate with DFT and backend teams for test insertion and ECOs.

● Generate GDSII for tape-out and support post-silicon bring-up if needed.

Required Skills & Qualifications

● Bachelor’s/Master’s degree in Electrical/Electronics/Computer Engineering.

● 3+ years of experience in ASIC/SoC physical design.

● Proficiency in EDA tools:

○ Synthesis: Synopsys Design Compiler, Cadence Genus

○ PnR: Cadence Innovus, Synopsys ICC2

○ STA: Synopsys PrimeTime

○ Physical Verification: Mentor Calibre, Cadence Pegasus

● Strong understanding of timing analysis, signal integrity, and power optimization.

● Experience with multi-clock domain designs and low-power design flows (UPF/CPF).

● Knowledge of foundry design rules for advanced process nodes (e.g., 7nm, 5nm).

Preferred Qualifications

● Experience with chiplet-based or 3D IC designs.

● Familiarity with high-speed interface physical design (PCIe, DDR, MIPI).

● Exposure to EM/IR drop analysis.

● Knowledge of design for manufacturability (DFM).

● Scripting skills (TCL, Python, Perl) for automation.

Interested guys, kindly share your updated profile to pavani@sandvcapitals.com or reach us on 7995292089.

Thank you.

Job Type: Full-time

Pay: ₹1,000,000.00 - ₹1,500,000.00 per year

Experience:

• Scripting: 3 years (Required)
• Physical Design: 3 years (Required)

Work Location: In person