665 Pcie Jobs - Page 12

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 4 to 7 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced IP Design Engineer to join our dynamic team. The ideal candidate will have a strong background in microarchitecture design, RTL design for complex IPs, and a deep understanding of AMBA or PCIe protocols. This role requires a hands-on approach and a commitment to delivering high-quality, reliable designs. Key Responsibilities: Lead the design and development of ground-up IP solutions, focusing on microarchitecture and RTL design. Collaborate with cross-functional teams to define and implement design specifications and requirements. Ensure the quality and performance of designs through rigorous PLDRC and synthesis processes. Develop and maintain detailed documentation for design processes and methodologies. Troubleshoot and resolve complex design issues, ensuring timely and effective solutions. Stay current with industry trends and best practices in IP design and related technologies. Qualifications: 7-10 years of experience in IP design, with a strong focus on microarchitecture and RTL design for complex IPs. Extensive hands-on experience with AMBA protocol or PCIe protocol. Proficiency in PLDRC and synthesis tools to ensure high-quality design outputs. Strong understanding of digital design principles and methodologies. Experience with design verification and validation processes. Excellent problem-solving skills and the ability to work independently and in a team environment. Strong communication and interpersonal skills. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Preferred Skills: Experience with industry standard design flow tools. Knowledge of ASIC design flows. Familiarity with scripting languages such as Python for automation. Experience with version control systems like Git, clearcase. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrs Very strong experience with Verilog, System Verilog and UVM Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM. Working experience on scripting and automation Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratch Strong base knowledge on digital design, blocks/components Strong debugging skills and Good knowledge of assertions and functional coverage coding and closure. Good knowledge on code coverage analysis and closure. Good knowledge of any scripting language Strong documentation and presentation skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support.Responsibilities:Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality.Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation.Minimum Qualifications:Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.8+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog/UVM.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications:Experience with Low power design verification, Formal verification and Gate level simulation.Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value addExperience in scripting languages (Python, or Perl).

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: We are seeking an experienced Embedded Linux Engineer with deep expertise in Distributions such as OpenWRT or Yocto, Linux kernel driver development, particularly in display panel drivers and embedded system integration. The ideal candidate should have hands-on experience with various kernel subsystems, DRM / FB frameworks, PCIe, and bootloader on UI frameworks (e.g., Qt, Wayland) on embedded devices. Proficient in bootloaders (e.g., U-Boot), kernel configuration, and initramfs management. This role also requires strong problem-solving skills and the ability to develop tools in Python to support embedded platforms. Proven track record in debugging memory leaks, performance issues, power management and complex field issues. Exposure to CI/CD pipelines and automated testing frameworks for embedded devices is a plus. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

IP/SOC Verification ,Design & Verification Failure Debugging Skills Verilog, System Verilog, & UVM Functional Coverage Development, & Coverage Closure PCIe, Ethernet, CXL, USB, CAN, LIN, FlexRay, AXI, AHB, APB Concepts in Digital Design

SMTS SOC Architect PCIe/CXL/UAL/DMA THE ROLE: AMD-Xilinx is looking for a SMTS SoC Architect to join the team in defining the next generation of Adaptive and Embedded SoCs. You will drive novel SoC architecture solutions across a wide range of applications, including Embedded Computing, AI/ML, Data Center, Communications, Automotive, and Aerospace, in close collaboration with customers, partners, product planning, SoC and IP architects, and design & verification teams. THE PERSON: As a SMTS SoC Architect you will help drive new architecture initiatives that leverage the state-of-the-art PCIe, CXL, and Confidential Compute technologies and standards. You will exercise your deep technical expertise and excellent communication skills to collaborate with design and product planning with an eye towards delivering innovative and highly competitive adaptive accelerators and embedded computing solutions. KEY RESPONSIBILITIES: Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over PCIe, UAL or CXL. Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric. Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors. Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets. Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and external CPUs. Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase. PREFERRED EXPERIENCE: Strong technical background architecting SoC and I/O subsystems involving PCIe, PCIe-DMA engines, or CXL. Deep technical knowledge of the PCIe or CXL protocol specifications, and how mandatory and optional protocol features are leveraged in PCIe or CXL devices. Domain expertise in embedded computing, aerospace & defense, data-center, networking, or automotive industries. Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPUs. Knowledge of bridging and ordering rule enforcement between on-chip protocols such as AXI, and off-chip protocols such as PCIe desired. Knowledge of ARM Processors and AXI Interconnects desired. Knowledge of FPGA and AI/ML Accelerators desired. Knowledge of boot, security, debug, telemetry and RAS desired. ACADEMIC CREDENTIALS: BS/MS/PhD in electrical or computer engineering or related field. LOCATION: Hyderabad, India #LI-MK1

We are seeking a Senior Engineer, who understand embedded NAND system design and firmware algorithms in order to create a test validation plans and implement them in modern object oriented languages. Work closely with the system architects and the firmware team to develop Validation plans, test bench and test cases Develop an overall validation strategy including defining validation infrastructure and validation methodology Debug the firmware and expose design issues Define and design functional tests required to meet customer needs Review SanDisk UFS/eMMC embedded NAND validation requirements and influence future SanDisk product design for debug and test Work with customers to understand field bugs and to enhance the validation coverage Interface with all key stakeholders to ensure product validation meets customer expectations and needs Qualifications Technical and analytical skills required In depth understanding of firmware algorithms used in any NAND Flash based storage devices (SSD, eMMC, UFS, SD, USB Flash drives) or other storage devices

As an SSD Validation Engineer at Micron Technology, Inc., your responsibilities will include: Define Test Plan, test cases and develop Test Scripts to validate SSD FW for Micron NAND based Systems and Solutions. Test areas will span across Functional, System level and Customer Qual centric tests. You would exhibit high degree of competency in understanding NVMe/PCIe specifications, NVMe Cloud SSD Specifications, along with understanding Customer specific requirements. You will be working in partnership with the Micron s Hyperscale/Datacenter customers throughout the Product Life Cycle to improve the cycle time and customer quality of Micron s SSD products. Be able to demonstrate success in communicating status, issues, concerns, strategies of programs and projects - including development of appropriate indicators. Must be able to deal with ambiguity and operate with little direction to meet defined goals. Must be able to work with and through others to achieve goals and task completion. Comprehend and articulate validation strategies, plans and status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidates true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: Lead End-to-End SoC DV execution and sign-off Define and drive improvements in DV processes for efficient and high-quality execution Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure, and gate-level simulations Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive SoC-level DV execution Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities Own and debug simulation failures to identify and resolve root causes Architect and implement simulation testbenches using UVM & C. Develop and execute test plans to verify design correctness and performance Collaborate with logic designers for thorough verification coverage and closure What Were Looking For Technical Requirement s: Bachelor s degree in CS/EE with 20+ years of relevant experience, or Master degree in CS/EE with 18+ years of relevant experience Experience in Leading core technical leads Must have experience in SOC/Subsys/IP level verification of ARM-based SOC and experience in ARM boot sequences Must have knowledge of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, HBM, PCIE, Ethernet and USB. Experience coding UVM SOC/Subsys/block level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing. What Were Looking For Technical Requirement s: Bachelor s degree in CS/EE with 14-18 years of relevant experience, or Master degree in CS/EE with 12-16 years of relevant experience Must Lead a team of 4-6 engineers Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

About this opportunity Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills? We are looking for an FPGA Designer to join the Ericsson Silicon organization. You will work with a group of dedicated engineers passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team developing and integrating complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do - Design and implement FPGA-based Radio and RAN Compute solutions - Develop and optimize FPGA designs for performance, power, and cost-efficiency - Collaborate with hardware and software engineers to integrate FPGA solutions into larger systems - Apply industry-standard tools and methodologies for FPGA development and implementation - Research and stay updated on the latest advancements in FPGA technology, including academia and industry trends in AI and Machine Learning - Document design specifications, test procedures, and results - Participate in design reviews and contribute innovative ideas to improve FPGA solutions You will bring To be successful in the role you must have: - 5+ years of experience in FPGA development - Comprehensive knowledge of: - FPGA technology, design environments, and design methodologies - FPGA design tools (e.g., Vivado, Quartus, or similar) - Hardware description languages (HDL), such as Verilog or VHDL - Experience with various communication protocols DDRX, AXI4, PCIE, SPI, I2C, embedded processing - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - Familiarity with hardware architecture and digital signal processing - Excellent problem-solving and analytical skills - Excellent English verbal and written communication skills - High self-motivation and the ability to work independently while being a great teammate - A track record of successful cross-team and cross-site cooperation - A Masters degree in Electrical or Computer Engineering or equivalent Primary country and city: India (IN) || Bangalore Req ID: 768579

About this opportunity Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills? We are looking for an FPGA Designer to join the Ericsson Silicon organization. You will work with a group of dedicated engineers passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team developing and integrating complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do - Design and implement FPGA-based Radio and RAN Compute solutions - Develop and optimize FPGA designs for performance, power, and cost-efficiency - Collaborate with hardware and software engineers to integrate FPGA solutions into larger systems - Apply industry-standard tools and methodologies for FPGA development and implementation - Research and stay updated on the latest advancements in FPGA technology, including academia and industry trends in AI and Machine Learning - Document design specifications, test procedures, and results - Participate in design reviews and contribute innovative ideas to improve FPGA solutions You will bring To be successful in the role you must have: - 5+ years of experience in FPGA development - Comprehensive knowledge of: - FPGA technology, design environments, and design methodologies - FPGA design tools (e.g., Vivado, Quartus, or similar) - Hardware description languages (HDL), such as Verilog or VHDL - Experience with various communication protocols DDRX, AXI4, PCIE, SPI, I2C, embedded processing - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - Familiarity with hardware architecture and digital signal processing - Excellent problem-solving and analytical skills - Excellent English verbal and written communication skills - High self-motivation and the ability to work independently while being a great teammate - A track record of successful cross-team and cross-site cooperation - A Masters degree in Electrical or Computer Engineering or equivalent Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768579

Job Title : SoC Architecture & RTL Engineer Company Overview Morphing Machines is a fabless semiconductor company focused on developing dynamic real-time reconfigurable RISC-V compliant dataflow accelerators. Our innovative technology aims to revolutionize hardware acceleration for high-performance computing and energy-efficient systems. Job Summary We are seeking a highly experienced SoC Architecture & RTL Engineer to design, implement, and optimize complex digital systems for next-generation computing platforms. This role offers the opportunity to work on cutting-edge SoC architectures involving high-speed interfaces and industry-standard protocols. Key Responsibilities Design and develop SoC architecture and RTL for complex digital systems. Work on CPU, GPU, and DSP pipelines, cache coherence protocols, and network-on-chip (NoC) designs. Integrate and validate PCIe, CXL, DDR, Ethernet, and other high-speed IPs. Ensure compliance with industry-standard protocols such as AXI, TileLink, PCIe, UCIe, and CXL. Perform simulation, synthesis, and optimization to meet performance and power targets. Collaborate with cross-functional teams for silicon delivery. Debug and resolve design and integration issues. Continuously explore and adopt new tools, methodologies, and technologies. Required Skills and Qualifications Bachelor s or Master s degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. 10+ years of experience in SoC architecture and RTL engineering. Strong expertise in digital design concepts, computer architecture, and hardware description languages (Chisel, Verilog, or VHDL). Hands-on experience with PCIe, CXL, DDR, Ethernet IPs. Experience with AXI, TileLink, PCIe, UCIe, and CXL protocols. Proficiency with digital design tools, simulation, and synthesis flows. Excellent problem-solving, communication, and teamwork skills. Ability to work independently in a fast-paced environment. Preferred Skills Experience in CPU/GPU/DSP core pipeline design and cache coherence protocols. Exposure to network-on-chip (NoC) architectures. Familiarity with power and performance optimization techniques. What We Offer Opportunity to work on innovative semiconductor technology. Collaborative, flexible, and inclusive work environment. Competitive compensation package. Exposure to cutting-edge hardware-software co-design challenges. Apply Now

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Lattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time individual contributor position located in Pune, India. The role will focus on RTL design and full chip integration and projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc. The role requires to work with architect and micro-architect team to understand define design specifications The successful candidate will be open and willing to both (a) teach best-known-methods to an existing design team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student. Accountabilities: Serve as a key contributor to RTL design efforts. Drive logic design of key blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality. Ensuring design quality through assertions, checkers, and scripting. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 5+ years of experience in driving logic design across a multitude of silicon projects. Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP. Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus. Familiarity with FPGA designs, use-cases, and design considerations is a plus. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry s technology leadership. An opening exists for Technical Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you wont just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment youd like to participate in, wed like to hear from you! As a Technical Staff Design Engineer, your job will entail the following: Lead the Design planning of pad rings and package substrates, bump pattern construction. Dynamically define and optimize pad ring connectivity. Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,) Interface with and support Architect, PD, PE, technology development and foundries teams. Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds. Additional responsibilities include: Collaborate closely with the Manager to define team structure, skill requirements, and hiring strategy for the local IP development team. Support and participate in end-to-end recruitment activities, including job description creation, candidate screening, interviews, and onboarding. Help identify and engage top technical talent through various sourcing methods in alignment with project and business goals. Assist in establishing a strong, high-performance team culture by supporting team integration, training, and knowledge-sharing initiatives. Work cross-functionally with HR, Talent Acquisition, and Engineering leadership to ensure a streamlined hiring process and effective team ramp-up. Contribute to the development of a scalable team that aligns with long-term IP roadmap and organizational growth. Requirements/Qualifications: B.S or M.S degree in electrical engineering with 12+ years of related experience Prior experience in IC and multicore SoC designs Experience with front-end CAD tools (eg. top-level I/O planning tools) is required. Experience with Verilog/System Verilog is required Familiarity with Verilog models and Liberty files Experience in Fin-Fet technologies is a plus. Scripting experience or knowledge is a plus. Excellent analytical, communication (written and verbal), and documentation skills Excellent problem solving and debugging skills. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

The Opportunity Were looking for the Wavemakers of tomorrow. Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semis expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators. What youll do: Own the end-to-end verification of new customer features Review design specifications and devise verification plans Build testbenches and analyze test failures to uncover design bugs Facilitate bit-matching of RTL design and MATLAB system models Integrate 3rd party VIPs for compliance testing of standard protocols Build releases of our design IP for customers Support post-silicon validation and bring-up activities Take on opportunities to lead, plan, and coordinate tasks with team members Collaborate closely with Design, Systems, Analog, FW, and PD teams Contribute to the continuous improvement of verification methodologies and processes What youll need: 5+ years of ASIC design verification experience An applied understanding of UVM and verification techniques Experience with constrained-random verification in SystemVerilog and UVM Formal Verification, and Power-aware UPF verification techniques Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Job_Description":" 8+ years of overall software engineering experience with 7+ years developing Networking and Hardware based Firewall firmware solutions. 5+ years\u2019 people leadership and team building experience with passion for bringing out the best in a team and helping people grow in their careers. Strong academic credentials with a master\u2019s degree in CS / EE, Mathematics, or other quantitative area of study Experience delivering high-performance NIC drivers in Linux and firmware implementation to support multi-ring architecture. Strong PCIe NIC background to design optimal Rx /Tx data transfer over PCIe, Experience with SR-IOV /virtio based Virtualization Implementation is a big plus! Good experience with one or more of fast path implementations - DPDK, eBPF, XDP Control and Data Path implementation of Firewall using ip tables including offload of Firewall functionality. Hands-on experience with KTLS / DTLS Design and Implementation including HW offload of TLS, IPSec HW Offload using Linux XFRM framework are desirable. Substantial and proven C and Python programming knowledge Proven ability to work with cross-functional teams in different locations. ","

System Validation engineers in this group are responsible for driving validation specifications & methodology and deliver on the validation of IPs for the next generation of compute solution. .You will work closely with architecture, design, verification, modelling, performance analysis, SW development, Emulation and FPGA and Board development engineers. Responsibilities: Work with project team to understand, review the system requirements and deliver emulator testbench specifications. Key responsibilities will include owning the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc) in emulation environment. Will guide other members of the team as needed to enable the successful completion of project activities Required Skills and Experience : Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering - although other degrees will be considered with relevant work experience You will need experience of Emulation and system level validation for IPs and sub-systems and ASIC products. Emulation build skills and knowledge for a subsystem in at least one emulation system is required. Execution of the design in emulation platform and knowledge of hardware and software interplay is required. You possess the knowledge of Validation test content using C, C++ etc and how they can be performed in an emulation-based system. Expertise on hardware behavioral language (Verilog, System Verilog) Exposure to producing validation specifications and documentation describing sophisticated designs Ability to work under time-scale pressure and meet ambitious targets without compromising on quality Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator. Practical experience of working on Processor based system designs Nice To Have Skills and Experience : Demonstrated understanding of CPU/ GPU subsystem in SoC environment and proven expertise in owning validation requirements & Validation Plan. Hands on Experience in validating multiple sub systems for ASICs/ SoCs in system environment ( across Emulation, FPGA and Development/Eval board), owning all phases of validation ( Test development, Execution and Debug) for owned sub systems. Understanding of SoC security aspects

Project description The client is a leader in the space of firmware/embedded development. Market leader with cutting edge technology. Responsibilities Drive the hands-on development of firmware solutions, ensuring innovation and efficiency Employ strong C language programming skills to create high-quality and reliable firmware Optimize and enhance functionalities related to BIOS, power management, and PCIe technologies Apply in-depth knowledge of UEFI BIOS, ACPI, and AGESA to contribute to advanced firmware development Lead and actively contribute to the development of platform BIOS, ensuring compatibility and optimal system performance Navigate the entire firmware development lifecycle, from conceptualization to release, ensuring efficiency and quality SkillsMust have Very strong in C language programming and debugging Working knowledge of git/Gerrit 7-10 years of experience in hands-on firmware development Good understanding and experience with BIOS, power management and PCIe Good knowledge SoC power management CPU/Device power states, hot-plug etc Strong knowledge of UEFI BIOS, ACPI. AGESA knowledge is a big plus Nice to have Bachelor's degree in computer science engineering from a reputed college Master's degree from a reputed university is a big plus

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

About Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities. Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Role - Baremetal Test Development Engineer - Mobile SoC: Notice - Immediate to 20 Days Experience - 7-20 Years Employer - Tessolve Semiconductors Job Location : Bangalore ( Work from office ) Note - Peoples whose below skills are not met kindly ignore this apply only it it meets your skills What you'll do Proficiency in C and Assembly programming* for embedded systems. Experience with firmware development* and debugging on baremetal or RTOS environments. Strong understanding of JTAG and other hardware debugging interfaces. Hands-on experience with at least two SoC subsystems:* CPU, GPU, multimedia, TPU, PCIe, or USB. Familiarity with SoC architectures* and low-level hardware/software interaction. Experience with test automation* using Python or Bash is a plus. Excellent problem-solving skills and attention to detail. Strong communication and teamwork abilities. Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries ( Tessolve ) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. If you receive any such communication, we strongly advise you to refrain from making any payments and to promptly report the incident to us at hr@tessolve.com. Tessolve is not responsible for any losses incurred due to such fraudulent activities Interested candidates pls send me your updated resumes to shreyas.ramesh@tessolve.com / References are welcome Thanks, Shreyas. R TA - Team , Tessolve

Candidate should have experience in Software development, tools development role, firmware development role or validation tools development.Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He/She will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical ExpertiseVery proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++. Computer Architecture KnowledgeIn-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache CoherencyExperience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and ConceptsAtleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator