665 Pcie Jobs - Page 10

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment. Basic Qualifications: Bachelor s degree or advanced diploma in Electrical Engineering (EE) Required Experience: 5+ years of experience in high-speed analog IC layout using Cadence Virtuoso Prior experience with BiCMOS layout is strongly preferred Proven experience handling at least one chip top-level through tapeout Proficiency in layout extraction and parasitic analysis for high-speed circuits Awareness of EMIR and antenna DRC rule-compliant layout practices Experience with Cadence SKILL and TCL scripting is highly recommended We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Technical Leader: C , Platform Development, Kernel, device driver,PCIe, i2c Meet the Team The Cisco Distributed System Engineering (DSE) group is at the forefront of developing products that power the largest networks in the world. The networking industry is going through a massive transformation to build the next generation infrastructure to meet the needs of AI/ML workloads and continuously increasing internet users and application. We are uniquely positioned to capture that market transition. This team builds products by harnessing the potential of open-source technologies while pushing the boundaries on Systems and Silicon Architecture. They are the developers and leaders who are passionate about tackling complex technology, building large scale distributed systems and comfortable working with open-source communities and technologies. Your Impact You will be involved with a fast-paced work environment and responsible for end-to-end product development and production support. As a technical lead, you will be involved on the following activities. Software Development & Integration: Lead the design, development, and deployment of software solutions leveraging SONiC to interface with hardware infrastructure and platform-level components. Develop and maintain platform adaptation layers for seamless integration between SONiC and underlying hardware (e.g., ASICs, BMC, and other platform elements). Collaborate with hardware teams to enable optimal hardware-software interactions and expose hardware capabilities through SONiC interfaces. Write, review, and optimize code for critical system modules, drivers, and APIs supporting high-performance data planes and control planes. System Architecture and Design: Define the technical architecture to integrate SONiC with platform infrastructure, ensuring scalability and high availability. Design robust interfaces between SONiC and platform-specific management/control modules (e.g., telemetry, diagnostics, and security components). Lead efforts to optimize resource utilization, power efficiency, and operational stability of the network platform. Leadership and Mentorship: Provide technical direction to the development team, mentoring junior and mid-level engineers on software engineering best practices and advanced networking concepts. Coordinate cross-functional activities between software, hardware, QA, and systems integration teams. Drive code reviews, technical discussions, and issue resolution to ensure timely and quality deliverables. Collaboration and Stakeholder Engagement: Act as a key liaison with open-source SONiC communities, contributing to upstream development and leveraging community innovations. Collaborate with product management and customers to understand use cases, gather requirements, and align deliverables with business objectives. Lead the evaluation and adoption of new tools, technologies, and methodologies to accelerate development and testing cycles. Minimum Qualifications Around 15 years of experience in software development within the networking or telecommunication industry Software development experience with Linux based platforms or other like network operating systems such as SONiC Experience with platform infrastructure such as ASIC drivers, NPU, BMC, Optics and network OS development Experience working with virtualization, containerization, and orchestration frameworks such as Docker, Kubernetes and/or similar Experience leading teams or technical projects in a complex development environment Preferred Qualifications Experience in CI/CD pipelines and automated testing frameworks Experience with platform level security requirements and compliance frameworks Understanding of telemetry systems and software-defined networking (SDN) Exposure to SONiC or experience working with the SONiC open-source community Knowledge of hardware abstraction layers and SDKs from major networking silicon providers (such as Broadcom, Marvell, Mellanox etc)

We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop and maintain Linux device drivers (Multimedia/PCIe) and Linux-based applications. Design and implement embedded software in C with focus on MMU, cache policies, and system performance. Debug and troubleshoot issues in both kernel and user space using appropriate debugging tools. work on Linux driver development and Linux application programming. Collaborate on integration of protocols such as PCIe, Multimedia, Ethernet, TCP/IP, I2C, and DMA framework. * Write and maintain Makefiles for build automation. Optimize and debug software for embedded Linux systems. Skills Must have 2-5y exp Proficient in C and embedded systems. Experience in Linux driver development (Multimedia/PCIe) and application development. Multimedia/PCIe driver development experience. Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills at kernel and user space and exposure to different debugging tools Knowledge on Multimedia, PCIe, Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Nice to have Hands-on experience with Configuration Management tool like GIT, Perforce. Have an interest to constantly learn and share new findings. A quality mindset, ability for strategic thinking and a drive to always improve. Self-motivated

Project description The client is a leader in the space of firmware/embedded development. Market leader with cutting edge technology. Responsibilities Drive the hands-on development of firmware solutions, ensuring innovation and efficiency Employ strong C language programming skills to create high-quality and reliable firmware Optimize and enhance functionalities related to BIOS, power management, and PCIe technologies Apply in-depth knowledge of UEFI BIOS, ACPI, and AGESA to contribute to advanced firmware development Lead and actively contribute to the development of platform BIOS, ensuring compatibility and optimal system performance Navigate the entire firmware development lifecycle, from conceptualization to release, ensuring efficiency and quality Skills Must have Very strong in C language programming and debugging Working knowledge of git/Gerrit 5-12 years of experience in hands-on firmware development Good understanding and experience with BIOS, power management and PCIe Good knowledge SoC power management CPU/Device power states, hot-plug etc Strong knowledge of UEFI BIOS, ACPI. AGESA knowledge is a big plus Nice to have Bachelor's degree in computer science engineering from a reputed college Master's degree from a reputed university is a big plus

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards Skills Must have 5-12 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash.. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop System Verilog/UVM-based testbenches for block-level and system-level verification. Write and execute UVM test cases to verify functional correctness of RTL designs. Perform detailed functional coverage and code coverage analysis, and drive coverage closure. Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution. Collaborate with cross-functional teams to ensure successful verification closure within project timelines. * Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred). Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging. Document verification plans, test specifications, test reports, and maintain traceability. Skills Must have 4-6y exp SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Nice to have Experience with python or any other scripting language is a plus

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Hardware Design - 5-8 years of experience Job Location : Whitefield ,Bangalore. What you ll do Leading the design,development, and implementation of high speed boards for servers, includingprocessors, memory, storage and network interfaces. Experience in full HDLC likeschematic design, PCB layout,SI-PI, mechanical and software integration. Experience in High Speed boarddesign with interfaces like PCIe 5.0,LPDDR4/5, SSD s,M.2,U.2 NVMe, SATA, USB,Ethernet etc Understanding customerrequirements, translating them into technical specifications, and working withother departments to ensure a robust and scalable solution Who you are Hands on experience in serverclass of board design with AMD or Intel GPU s and FPGA, with high speedinterfaces like PCIe 5.0,LPDDR4/5, SSD s,M.2,U.2 NVMe, SATA,CXL,USB,Ethernet.etc. Hands onexperience in Hardware Development Life Cycle like design, bringup, testing and validation of boards,functional testing, trouble shooting, debugging and Failure analysis. Experiencein at least one complete project starting from the high-level design to thefinal validation. Should beable to independently handle schematic design, design analysis and reviewcoordination with peer designers. Mentoringand guiding a team of hardware engineers, providing technical expertise andsupport, and ensuring team members adhere to industry standards. Collaboratingwith cross function teamin managing PCB layout, SI-PI simulations, Software development, mechanical , thermal, siliconIP Validation, BIOS and Driver Development/QA etc. and other stakeholders to ensure a cohesive andefficient system design. Experiencewith relevant design tools like Altium and Orcad. Handon experience in using instruments like high speed Oscilloscopes, DMM,electronic loads etc. Should be able to develop the board bring-up plan,be able to identify the test equipment required and execute independently. Experiencein preparing and reviewing hardware design documentation and issueinvestigation reports. GoodCommunication and interpersonal skills Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any losses incurred dueto such fraudulent activities

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group develops transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and growing further. This is your Role Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesized design using Verilog/System Verilog. Required Experience: We seek a graduate with at 1-5 years of relevant working experience with (BE/BTech/ME/MTech/MS) from a reputed engineering college. We value your experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification. Good understanding of IP Verification Methodologies, Verification procedures and practices are plus! Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc We value expertise in Verilog, SystemVerilog, and SystemC, as well as experience in developing RTL for FPGAs, ASICs, and IPs, as this will greatly contribute to the quality of our products. We expect candidates to be able to build verification test plans and environments, develop test cases, utilize VIPs, and efficiently debug defects identified during verification processes. We consider exposure to object-oriented programming languages like C++ an advantage, and experience in scripting languages such as Perl will also be valuable in automating tasks and improving efficiency. You need to engage with customers for Deployment and R&D assistance. We've got quite to offer, how about you We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, colour, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. At Siemens, we are always challenging ourselves to build a better future. We have some of the most inquisitive minds working across the world, re-imagining the future and doing extraordinary things. #LI-EDA

Looking for Siemens EDA ambassadorsLead Software Engineer for Product Validation and Customer support for PowerPro We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and betterJoin us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by growing efficiency and customer satisfaction Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: We are in DDCP (Digital Design Creation Platform group) which include top industry tools like Tessent, PowerPro, Catapult, Aprisa. We are part of DPRS (Devops, Product, Release & Support group) inside DDCP which works on cutting edge tools like PowerPro. Our team is responsible for Product Validation, Customer Support & Release work for PowerPro tool. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Lead 1-2 junior folks or Intern. guide them and help them in day-to-day activities. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Worked on designs to apply power solutions, UPF etc. Different Tool knowledge like Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, DC etc. Worked in EDA CAD team for RTL Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. Team leader We’ve got quite a lot to offer. How about you A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday Accelerate transformation #li-eda #li- Hybrid

Job description Design Verification Engineer (4 to 15 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 4 to 15 Years Openings: 4 Positions Preferred - Immediate to 45 Days (Notice Period) ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

Key Responsibilities: Develop and execute comprehensive verification plans for SoC and NoC systems Design and maintain test benches using SystemVerilog and UVM Perform functional, performance, and low-power verification Debug and resolve design/verification issues independently Work with high-speed protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Ensure thorough coverage and compliance with design specifications Collaborate with cross-functional teams including RTL, DFT, and architecture Required Skills: 7+ years of hands-on experience in SoC/NoC verification Strong expertise in System Verilog, UVM, and scripting (Python/Perl/TCL) Experience with simulation tools like VCS, Questa, or Incisive Solid understanding of interconnect protocols: AXI, CHI, PCIe, Ethernet, etc. Familiarity with coverage analysis and debugging tools Strong analytical and problem-solving skills Preferred: Experience with CXL or UCIe protocols Exposure to formal verification or emulation tools is a plus

Design Verification Engineer - Specialised in Protocol like; PCIe/Ethernet/DDR/LPDDR/HBM Location: Noida, UP / Bangalore, India Experience: 3-10 Years Job Description: Experience in interconnect protocol PCIe/ Ethernet. Experience in Memory protocol DDR/LPDDR/HBM; HBM is preferred. AXI/ACE/CHI understanding, [AXI is must] Understanding of DMA usage. Strong in SV/UVM. Experience in the usage of standard VIP in TBs (preferably Synopsys) AI/ML network understanding (good to have). Additional knowledge of perl/tcl scripting will be an advantage. Must Bachelors Degree in Electrical, Electronics or Computer Engineering

We are seeking an experienced and technically strong Probe Card and Boards Design Lead to drive the development of probe cards, load boards, and interface hardware for ATE-based testing of SoCs, MCUs, and mixed-signal ICs. The ideal candidate will have deep expertise in board-level hardware design, probe card specifications, signal/power integrity, and vendor coordination, with the ability to lead a cross-functional team through development, validation, and production support. Key Responsibilities: Own the end-to-end design and development of probe cards and test interface boards (load boards, DUT boards) for wafer-level and package-level ATE testing. Define probe card specifications based on die pad layout, test requirements, and ATE platform constraints. Collaborate with DFT, validation, and product engineering teams to capture test interface needs and ensure compatibility with test plans. Perform board-level schematic and layout reviews for signal integrity, power integrity, and mechanical constraints. Coordinate with probe card vendors and OSAT partners for fabrication, delivery, and debug. Drive characterization of signal paths, trace impedance, and routing quality for high-speed interfaces (e. g. , LPDDR, PCIe, USB). Define test socket, pogo pin, connector, and mechanical fixture requirements. Lead bring-up, debug, and issue resolution of probe cards and load boards on ATE (Teradyne UltraFlex, Advantest T2000, etc. ). Manage timelines, design reviews, and hardware readiness for silicon validation milestones. Qualifications B. E. /B. Tech or M. E. /M. Tech in Electronics or Electrical Engineering. 13+ years of experience in ATE hardware interface design, probe card development, or board-level hardware design. Strong knowledge of probe card technologies (MEMS, vertical, cantilever), pitch considerations, and DUT layout alignment. Proficient in PCB design tools (e. g. , Cadence Allegro, Mentor Xpedition) and schematic capture. Experience with high-speed signal routing, power delivery, controlled impedance, and board stack-up. Solid understanding of ATE platform requirements (e. g. , load board layer count, impedance control, pin mapping). Familiarity with mechanical design constraints and fixture interface. Hands-on experience in lab debugging and ATE test floor support. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Seeking a technically strong and proactive Post-Silicon System Validation / Functional Validation Lead to drive the planning, execution, and debug of system-level validation of IP and SoC/MCU designs. This role is critical in verifying functional correctness, feature compliance, performance, and robustness of silicon devices across use cases, voltage/temperature corners, and real application conditions. Key Responsibilities: Lead post-silicon system and functional validation of complex SoCs/MCUs. Develop and own validation plans, test strategies, and feature coverage matrices aligned with architecture and design specifications. Work closely with architecture, design, verification, firmware, and product teams to identify validation scope and execution path. Set up bring-up environments on evaluation boards, FPGA/emulation platforms, and validation platforms. Validate system functionality (boot, interfaces, power management, interrupts, etc. ) under various stress, corner, and performance scenarios. Develop test content, diagnostic tools, automation scripts, and custom firmware to exercise system features. Drive silicon debug, root cause analysis, and collaborate on corrective actions with design and DFT teams. Analyze test logs and data, track bugs, and drive closure through structured validation cycles. Lead a team of validation engineers, assign tasks, and manage deliverables for tape-out schedules or customer milestones. Prepare validation reports, functional coverage summaries, and risk assessments for tape-out or production release. Qualifications Required skills and Qualification: B. E. /B. Tech or M. E. /M. Tech in Electronics, Electrical, or Computer Engineering. 13+ years of experience in post-silicon validation, system validation, or embedded SoC bring-up. Strong understanding of SoC architecture , ARM cores (A/M series) , peripherals , power/clock/reset , and low-power design techniques . Experience validating high-speed interfaces (e. g. , DDR, USB, PCIe, MIPI, Ethernet) and standard protocols (SPI, I2C, UART, CAN, etc. ). Proficiency in C/C++ or embedded programming for firmware development and test automation. Hands-on experience with lab tools (oscilloscopes, logic analyzers, power analyzers, thermal sensors). Familiarity with validation frameworks, debug utilities (JTAG, Lauterbach, OpenOCD), and issue tracking systems (JIRA, Bugzilla). Strong leadership, communication, and collaboration skills. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

3 years of experience Pre/Post Silicon Validation: Develop and deploy embedded diagnostic software for custom SOCs. Hands-on experience with FPGA, chip bring-up, etc. Expertise in working with and programming different chip peripherals. Hardware bring-up on SoCs, prototyping and emulation systems, Bare Board Bring Up Experience with the development of real-time embedded systems, microcontrollers, FPGAs, and ARM processors Substantial and proven C programming knowledge, CMSIS/Assembly Programming Strong background in highly resource-constrained, real-time, embedded environments Experience some of the popular MCU, e.g., ARM Cortex (M0, M55, A53), RISC-V Experience with various peripherals such as PCIe, USB, SDIO, SPI, I2C, I2S, GPIO, etc. Excellent debugging skills, including proficiency with oscilloscopes, logic analyzers, spectrum analyzers Experience in the use of modern software development tools,

We are looking for experienced RTL Integration Engineers to join our team and contribute to cutting-edge semiconductor designs. If you have a passion for SoC integration and front-end design methodologies, we want to hear from you! Key Responsibilities: Deliver RTL Subsystems and/or top-level SoC RTL across multiple projects Expertise in RTL database management, partitioning, and third-party IP integration Work with lint, DFT, UPF, synthesis, timing, and power analysis Address SoC integration challenges at both subsystem and full-chip levels Integrate Digital IPs such as PCIe, SDIO, USB, and ARM processors with protocol expertise Design top-level clock/reset circuits and manage memory selection/generation Join us and be part of a high-impact team shaping the future of semiconductor technology! Interested Drop your resume at info@silcosys.com #RTL #SoC #Integration #Semiconductor #Hiring #VLSI #Engineering #JobOpening,

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.,

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Core Switch Group (CSG) at Broadcom is the industry leader in cutting-edge networking ASICs, developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team is behind iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazines "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If youre a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium . Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring Bachelor s with 12+ years in emulation or post-silicon validation of networking ASICs. Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. Excellent communicator who thrives in a collaborative, fast-paced environment.

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AXI, AHB, APB, CHI, ACE Solid debugging in NoC, memory subsystems Proficiency in C/C++ Exposure to GLS (Zero delay, SDF, PA GLS) simulations is a plus Knowledge of memory protocols: LPDDR4, LPDDR5, DDR, HBM preferred Experience in PCIe, CXL, Ethernet protocols is a plus Scripting (Python, Perl) – good to have for automation and flow enhancements Desired Candidate Profile : 5+ years of experience in DV Must be proactive , with strong debugging & simulation skills Capable of working independently or as part of a dynamic team How to Apply : Email your CV to: Richa.smriti@orcapod.work , contact: +91 92349 19275

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Core Switch Group (CSG) at Broadcom is the industry leader in cutting-edge networking ASICs, developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team is behind iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazines "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If youre a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium . Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring Bachelor s with 12+ years in emulation or post-silicon validation of networking ASICs. Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. Excellent communicator who thrives in a collaborative, fast-paced environment. .

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its RD center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Packet Processing Design: Design and architect solutions for high-speed networking device, focusing on latency optimization, and quality of service (QoS) support. Prior experience with CAMs, and routing tables. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation to ensure functionality and reliability. Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics. Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet. Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including hardware engineers, firmware developers, and system architects. Qualifications ME/BE with a minimum of 8-15 years of experience. Working knowledge of system Verilog, and Verilog is Mandatory . Prior experience with ownership of memory subsystems. Proven expertise in designing and optimizing packet pipelining and QoS mechanisms, for high-speed networking devices. Solid understanding of ASIC design methodologies, including simulation, and verification tools (e.g. Synopsys, Cadence). Experience with Ethernet/PCIe networking protocols. Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its RD center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking a RTL Data Path Engineer to help define and implement our industry-leading Networking IC. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Data Path Design: Design and architect solutions for high-speed networking device, focusing on latency optimization, memory management, and quality of service (QoS) support. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation to ensure functionality and reliability. Performance Optimization: Analyze and optimize memory/buffering to improve performance metrics. Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet. Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including hardware engineers, firmware developers, and system architects. Qualifications BE/ME with a minimum of 8-15 years of experience. Working knowledge of system Verilog, and Verilog is Mandatory. Prior experience with ownership of memory subsystems. Proven expertise in designing and optimizing memory algorithms and QoS mechanisms, for high-speed networking devices. Solid understanding of ASIC design methodologies, including simulation, and verification tools (e.g. Synopsys, Cadence). Experience with Ethernet/PCIe networking protocols. Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences. Why Join Us At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. "},"