Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience of at least 9+ years Track record of first-pass success in ASIC development cycles Hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle At least 9+ years of hands on experience Preferred Qualifications Experience in development of UVM based verification environments from scratch Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet Experience working across and building relationships with cross-functional design, model and emulation teams

The job involves working on Cisco UCS AI Server platform development activities. This team develops Software and Firmware for Cisco UCS platforms. This includes development of Server BMC (a.k.a Cisco Coordinated Management Controller) Firmware, Software, tools and utilities. In this role, you will have the opportunity to lead the technical charter and provide technical vision for Baseboard Management Controller (BMC) activities. You will be part of the UCS AI Rack Server team, Bangalore, which is a key part of Ciscos Data Centre strategy. We are looking for hands-on Technical architects as applicants who strive in a fast paced start-up like environment. You will be part of a dedicated team and open communications, empowerment, innovation, collaboration and customer success are the foundations of the team. For further product info, please look at this link Responsibilities include: Senior Engineer in the AI Server BMC team Demonstrate a high degree of originality and innovation in design/development activities. Be a hands-on Engineer working across different architectures and environments. Work closely with Hardware Team for design, schematic review, hardware bring up and debug activities. Work closely with group of other architects/collaborators to define the complete design. Influence the design of interfaces between products to ensure interoperability. Design and develop software in a real-time Linux (or similar) OS environment for Cisco UCS server platforms. Design and develop system software to meet the specification of platform requirements. Comprehend newer, complex datacentre customer requirements and translating to engineering features. Who You Are Required Experience and Skills: Excellent Data Centre/Cloud platform engineering Expertise Excellent hands-on experience in Firmware, Device Driver and Embedded/Real time systems development. Good knowledge of x86 and ARM architectures. Very Strong Expertise in C and other programming language(s) expertise is a plus. Very Strong proponent of Design thinking and abreast of new architecture/design/development methodologies Excellent verbal and written skills and professional presentation. Desired Experience and Skills Experience in Server/Storage chassis platform technologies Hands on experience in management controller firmware development (BMC) and IPMI/Redfish. Experience in HW tools like JTAG debuggers, I2C analyzers, Oscilloscopes and flash memory programmers. Experience in Industry standard protocols like PCIe, NVMe, CXL and other Interconnect/Server technologies Experience with GIT/Bitbucket 8-12 Years of experience BE/BTech/ME/MTech in Electronics/Computer Science preferred.

Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills: 15+ years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such as PCIe, CXL. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skill1. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of datacenter industry technologies and their software stack.

Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 4-7 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas!

Looking for Siemens EDA ambassadors: Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 2-4 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas!

WHAT YOU WILL DO ESSENTIAL DUTIES AND RESPONSIBILITIES Develop firmware using C/C++ in multiple environments using latest standards: FPGA, Simulator, for NAND/eHDD (Enterprise Hard Disk Drive) products. Follow Agile methodologies in development. Create design documents pertinent to the various phases of firmware development. Youll be on a scrum team responsible for full stack embedded firmware development for enterprise products. This includes innovation, design, implementation and debug of data path, software algorithms, data structures, drivers needed for our large and complex software environment. Deliver on cutting-edge storage products with interfaces like SAS, SATA, PCIe. Work with cross functional teams to develop HDD products. Self-motivated to work both unsupervised and as part of an agile team. Collaborate to develop self and others within group. Understand end to end product lifecycle. Exposure to working with NAND devices and memory systems in general. Understanding of device characterization requirements and validation methodologies

This is a great chance to create a real impact by testing NVIDIA s DriveOS automotive operating system. As a highly skilled and motivated senior software developer, you will push the boundaries of testing and automation, shaping our verification strategy and influencing the future of our test automation systems. If youre passionate about self-driving technology and ready for a challenge, we want to hear from you! What you will be doing You will have a unique opportunity to be at the forefront of ensuring the flawless performance of NVIDIAs groundbreaking technology. Your contributions will directly impact the quality and reliability of our solutions, shaping the future of autonomous systems. In our fast-paced and dynamic environment, you will take on exciting challenges, including: Developing and refining test strategies and test plans for new features, ensuring our solutions meet the highest standards of excellence. Designing and implementing automated testing frameworks to enhance verification processes, driving efficiency and reliability in our testing pipelines. Collaborating with multi-functional teams to gain a deep understanding of customer use cases, project requirements, and feature specifications, ensuring alignment with real-world applications. Investigating, analyzing, and addressing issues found during testing, leading root-cause analysis and implementing effective solutions. Enhancing and optimizing QA processes, ensuring technical excellence while continuously improving quality standards. Providing mentorship and guidance to fellow team members, fostering a culture of collaboration, innovation, and technical excellence. Engaging with global teams across different time zones to deliver a seamless and exceptional user experience. Your expertise in testing and automation will be instrumental in shaping the success of NVIDIAs cutting-edge technology, ensuring we deliver world-class solutions to our customers. What we need to see To excel in this role, we are looking for candidates with the following qualifications: B. E / B. Tech / MS / MCA or its equivalent degree 3+ years of relevant experience in software development Experience in using AI coding assistants to improve coding efficiency and correctness Knowledge in Linux and/or QNX is required Strong embedded testing experience Strong Python skills, with the ability to write logical scripts/code from scratch and use automation frameworks Ability to read C/C++ and low-level code Excellent analytical skills for solving problems Strong interpersonal and communication skills are important An excellent teammate demeanor, passionate about autonomous driving and related fields. Ways to stand out from the crowd Experience in the Autonomous driving domain Proven understanding of Linux Kernel Internals, system software, Graphics, and Multimedia Concepts Proficiency in industry-standard I/Os such as Display, Resource Manager, Ethernet, CAN, PCIe, and PTP or equivalent experience LLM, GenAI Knowledge Intelligent machines powered by Artificial Intelligence computers that can learn, reason and interact with people are no longer science fiction. GPU Deep Learning has provided the foundation for machines to learn, perceive, reason and solve problems. Now, NVIDIA s GPU runs Deep Learning algorithms, simulating human intelligence, and acts as the brain of computers, robots and self-driving cars that can perceive and understand the world. Come be a part of this exciting world, at NVIDIA. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 2-4 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas!

Role & responsibilities Bachelor's/Masters Degree in Electronics/Computer Engineering. 6+ years of in-depth experience in x86 architecture and hardware design. System design experience is preferred. Experience in schematics design tool like concept HDL, and supporting physical/Layout design activity, hardware bring-up and validation will be required. Knowledge and design experience of DDR3/4, PCIe, SERDES Technologies, Ethernet along with High-speed PCB design and signal integrity will be advantage. Good experience in Board Bring-up, Hardware and System level debugging Good understanding of interfaces like DDR-2/3/4, PCIe, SerDes protocols Good experience on management interface like SPI, I2C Proven experience on preparation of Functional Specifications, Production Definition and taking ownership on Documentation Hands on with the usage of design tools from Mentor Graphics and Cadence Hands on with the usage of Digital Oscilloscope, Multimeters, test and measuring equipment

As an SSD Design Engineer at Micron Technology, Inc., Solid State Drive (SSD) team, you responsible for taking solid state drives from design to high volume manufacturing. This will involve product characterization, margin analysis, performance/power characterization, internal/external customer support, and manufacturing support. You will also be responsible for improving performance, improving testability, and identifying NAND/DRAM reliability issues Other areas of responsibility include electrical and physical failure analysis, implementation of new device qualifications, characterization development, and yield evaluation/improvement. Additional Responsibilities include, but are not limited to, the following: Perform Test Development/Analysis Develop and design test plans/scripts to evaluate new product features Evaluate existing test plans/scripts to improve test coverage and efficiency Identify and/or develop test tools to enable failure analysis and improve testability Perform Product Test and Failure Analysis Perform product testing to evaluate and support new product development Analyze failures to determine root cause of issues Drive issues to closure by interfacing/collaborating with other product development teams Verify Architecture specifications to test plan alignment by generating a Master Test Plan on each product Support Internal/External Customers Provide technical support (e.g. failure analysis, questions, etc.) to any internal or external customer as part of product development Provide Failure Analysis training to internal teams Support customer and internal audits Drive common debug strategy into individual programs Safety and Procedure Follow established policies and procedures Drive common processes across System Engineering Recognize and resolve safety or environmental issues, including assistance to develop appropriate procedures and documentation Use available resources to complete tasks in a safe and efficient manner For this position, you must have the ability to work in a team environment as well as the ability to work and maintain good relationships with worldwide suppliers and customers It is also essential that you have very good English verbal and written skills in addition to excellent documentation, leadership, and problem-solving skills. Technical capabilities should include: In depth knowledge of one or more interface standards such as SATA, SAS, and PCIe Understanding of NAND memory operation. Hands on experience with logic analyzers, bus analyzers and digital oscilloscopes. Programming experience in C and Python Familiarity with Windows, and Linux. The ability to drive engineering efforts through all aspects of new product development and system level debug. The ability to analyze problems, diagnose root cause, and apply corrective actions.

As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Basic qualifications Bachelor s/ Master s degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skill

Position: Platform firmware engineer (SI810T RM 3060) Essential duties and responsibilities: Understand memory product specifications, Front end protocols (PCIe, NVMe etc.) and design test bench and test cases in embedded firmware to support the verification and validation of memory products. Align the development and validation process with cross-functional teams. Create internal and external specifications, stay current with technology trends and roadmaps. Learn constantly, dive into new areas with unfamiliar technologies, and embrace the ambiguity of problem-solving. Apply critical thinking to the results/data of competitive analysis for product development. Work with cross-functional teams, including ASIC, Firmware, and Validation, to ensure seamless product development. Qualifications REQUIRED: Proven track record Experience with C/C++ in developing Embedded FW scripting automation using Python Proven ability to work as part of a global team in multiple geographies B.Tech. in Computer Science or Software / Computer / Electrical Engineering Requires 8-10 years of experience in RT / embedded systems architecture Multi-disciplinary experience, including Firmware, HW, and ASIC design Experience in using debug tools (JTAG, UART IEEE1500) PREFERRED: Knowledge of PCIe Gen5/6 technology is an advantage Previous experience with storage systems, protocols, and NAND flash - strong advantage SKILLS: Capable of developing wide system view for complex embedded systems Excellent interpersonal skills Strong can-do attitud

What You ll Do The job involves working on Cisco UCS AI Server platform development activities. This team develops Software and Firmware for Cisco UCS platforms. This includes development of Server BMC (a.k.a Cisco Coordinated Management Controller) Firmware, Software, tools and utilities. In this role, you will have the opportunity to lead the technical charter and provide technical vision for Baseboard Management Controller (BMC) activities. You will be part of the UCS AI Rack Server team, Bangalore, which is a key part of Ciscos Data Centre strategy. We are looking for hands-on Technical architects as applicants who strive in a fast paced start-up like environment. You will be part of a dedicated team and open communications, empowerment, innovation, collaboration and customer success are the foundations of the team. For further product info, please look at this link Responsibilities include: Senior Engineer in the AI Server BMC team Demonstrate a high degree of originality and innovation in design/development activities. Be a hands-on Engineer working across different architectures and environments. Work closely with Hardware Team for design, schematic review, hardware bring up and debug activities. Work closely with group of other architects/collaborators to define the complete design. Influence the design of interfaces between products to ensure interoperability. Design and develop software in a real-time Linux (or similar) OS environment for Cisco UCS server platforms. Design and develop system software to meet the specification of platform requirements. Comprehend newer, complex datacentre customer requirements and translating to engineering features. Who You Are Required Experience and Skills: Excellent Data Centre/Cloud platform engineering Expertise Excellent hands-on experience in Firmware, Device Driver and Embedded/Real time systems development. Good knowledge of x86 and ARM architectures. Very Strong Expertise in C and other programming language(s) expertise is a plus. Very Strong proponent of Design thinking and abreast of new architecture/design/development methodologies Excellent verbal and written skills and professional presentation. Desired Experience and Skills Experience in Server/Storage chassis platform technologies Hands on experience in management controller firmware development (BMC) and IPMI/Redfish. Experience in HW tools like JTAG debuggers, I2C analyzers, Oscilloscopes and flash memory programmers. Experience in Industry standard protocols like PCIe, NVMe, CXL and other Interconnect/Server technologies Experience with GIT/Bitbucket 8-12 Years of experience BE/BTech/ME/MTech in Electronics/Computer Science preferred.

Drive the hands-on development of firmware solutions, ensuring innovation and efficiency Employ strong C language programming skills to create high-quality and reliable firmware Optimize and enhance functionalities related to BIOS, power management, and PCIe technologies Apply in-depth knowledge of UEFI BIOS, ACPI, and AGESA to contribute to advanced firmware development Lead and actively contribute to the development of platform BIOS, ensuring compatibility and optimal system performance Navigate the entire firmware development lifecycle, from conceptualization to release, ensuring efficiency and quality Skills Must have Very strong in C language programming and debugging Working knowledge of git/Gerrit 3-10 years of experience in hands-on firmware development Good understanding and experience with power management Good knowledge Sof oC power management - CPU/Device power states, hot-plug etc Nice to have Bachelors degree in computer science engineering from a reputed college Masters degree from a reputed university is a big plus Good understanding and experience with BIOS and PCIe Strong knowledge of UEFI BIOS, and ACPI

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES andPHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3 + years of experience in Functional Verification of Processors or ASICs. Minimum 2+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Madhu to update ASICs specific skills Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Owning and Driving execution of subunits/unit level Verification Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Work with IBM Verification community to improve Verification methodology. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 + years of experience in Functional Verification of processors or ASICs. Minimum 9+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading teams Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification. Good understanding of the Server System

Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Preferred Qualifications 5+ Year of industry experiences in the following areas: - Good knowledge of processor-based design Power-aware verification, UPF, and CLP Strong understanding of CPU and assertion Formal verification experience is a plus Interested can share resume on Shubhanshi@incise.in

You would exhibit high degree of competency in understanding NVMe/PCIe specifications, NVMe Cloud SSD Specifications, along with understanding Customer specific requirements You will be working in partnership with the Micron s Hyperscale/Datacenter customers throughout the Product Life Cycle to improve the cycle time and customer quality of Micron s SSD products Be able to demonstrate success in communicating status, issues, concerns, strategies of programs and projects - including development of appropriate indicators Must be able to deal with ambiguity and operate with little direction to meet defined goals Must be able to work with and through others to achieve goals and task completion Comprehend and articulate validation strategies, plans and status

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model. Work on high speed SERDES interface verification such as PCIE but not limited to. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Work with FW team to convert DV sequence to FW drivers Support emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS. 5 or more years of experience in ORAN protocol design verification using reference models. Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks. Experiences in Cadence vManager for DV metrics extraction and regression Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch. Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based Experiences in GIT, JIRA, MS office suites Benefits: Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the worlds mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same. Intimate knowledge of Linux with a solid understanding of the kernel, kernel patches, kernel modules, static and dynamic libraries, root file system layout, and available features and functionality in many OSS packages. The ability to write and debug Linux device drivers with knowledge about mutexs, ISRs, user space versus kernel space drivers, mmap and other driver concepts. Familiar with bootloaders (uboot) with the ability to do initial board bring up. Prior experience with writing and debugging drivers for PCIe, I2C, SPI, UART. Familiar with CPU architectures, like ARM Proficient in C, C++, and Bash Familiar with testing and debugging software through unit test, GDB, and JTAG BDMs. Fundamental understanding of SCM, Packaging, and Build Systems like Makefiles, Git, Autotools, RPM, etc. Experience in one or more of the following: Buildroot, Yocto Linux Distro, Grub, ONIE, ZMQ, distributed messaging frameworks, TCP/IP, SDKs from Broadcom. Experience of having gone through full cycle of Software development multiple times across product lines and supporting multiple concurrent releases and HW targets. Grade Specific Intimate knowledge of Linux with a solid understanding of the kernel, kernel patches, kernel modules, static and dynamic libraries, root file system layout, and available features and functionality in many OSS packages. The ability to write and debug Linux device drivers with knowledge about mutexs, ISRs, user space versus kernel space drivers, mmap and other driver concepts. Familiar with bootloaders (uboot) with the ability to do initial board bring up. Prior experience with writing and debugging drivers for PCIe, I2C, SPI, UART. Familiar with CPU architectures, like ARM Proficient in C, C++, and Bash Familiar with testing and debugging software through unit test, GDB, and JTAG BDMs. Fundamental understanding of SCM, Packaging, and Build Systems like Makefiles, Git, Autotools, RPM, etc. Experience in one or more of the following: Buildroot, Yocto Linux Distro, Grub, ONIE, ZMQ, distributed messaging frameworks, TCP/IP, SDKs from Broadcom. Experience of having gone through full cycle of Software development multiple times across product lines and supporting multiple concurrent releases and HW targets.

TE Connectivitys R&D/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. They are responsible for product development, and qualification from market definition through production and release; assist in the qualification of suppliers for new products to ensure suppliers deliver quality parts, materials, and services for new or improved manufacturing processes; conduct feasibility studies, testing on new and modified designs; direct and support detailed design, testing, prototype fabrication and manufacturing ramp. The R&D/Product Development Engineering Teams provide all required product documentation including, but not limited to, Solid Model, 2D/3D production drawings, product specifications, and testing requirements. They create and modify detailed drawings and drafting or conceptual models from layouts, rough sketches or notes and contribute to design modifications to facilitate manufacturing operation or quality of product. Typical fields of expertise include: materials, mechanics and systems, electrical, optics, chemistry, software, automation systems, packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. Responsbilties: Drive SI design, simulation, and validation for next-gen high-speed interconnects (112G/224G PAM4, PCIe Gen6/7, Co-Packaged Optics) through the product development cycle. Conducting SI COE analysis, including o Performing signal integrity simulations and analysis for high-speed interconnect product development. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface. o Modeling the connector with the consideration of manufacture impact and application impact. o Providing solutions to the SI challenges. This includes identifying the problems, making research plan, developing new technologies, and training and sharing the findings to the SI community. Develop novel interconnect solutions by optimizing mating interfaces, lead frames, and PCB transitions for resonance-free, low-loss performance. Enhance bulk cable design & termination techniques to minimize skew, impedance mismatches, and signal degradation. Advance high-frequency testing methodologies beyond 67 GHz with innovative non-PCB-based test fixtures. Utilize AI & big data analytics for predictive SI modeling, auto-routing, and performance optimization. Optimize material selection & electromagnetic design to improve noise isolation, signal integrity, and high-frequency response. Collaborate with NPD teams & industry partners to influence SI strategies, technology roadmaps, and next-gen product designs. Represent TE at industry forums (IEEE, OIF, PCI-SIG, etc.) and contribute to next-gen SI standards. Should have total work experience of 3-8+years. Minimum of 5+ years of work experience in a signal integrity engineering role or related experience Minimum of 3+ years of work experience in connector development - Experience with interconnect design or experience with connector &/or cable/cable assembly design (high speed twinax cables, direct attach copper (DAC) cables) Demonstrated experience using Signal integrity analysis tools (Agilent ADS, Ansys HFSS or equivalent, 3D modeling tools) and testing equipment (including VNA, TDR and BERT). A solid understanding of statistical analysis and AI training. A solid understanding of SI knowledge, including electromagnetic theory and electrical circuit behavior Strong analytical capabilities to interpret simulation and lab data to identify issues and provide solutions to fix identified problem. Familiarity with printed circuit board design, fabrication and assembly. Familiar with material, manufacturing process, and manufacture inspection. Familiar with at least one programming language, such as Matlab, python, C++, VB, etc. Excellent verbal and written communication skills Ability to work in a global environment able to accommodate varying time zones, fluent in English (verbal/written), able to collaborate with individuals across geographies DESIRED SKILLS Printed circuit board design (proficient in Altium a PLUS), fabrication and assembly (AutoCAD) Communication systems (high-speed servers, switches, routers, storage) Signal conditioning techniques (equalization, amplification) SixSigma methodologies or other strong data analytics background a PLUS. Experience in project leadership, especially as it applies across design, development & manufacturing teams Direct customer design and support experience Application and test knowledge of high-speed devices and equalization techniques Design experience with high-speed servers, switches, routers, storage, antenna, RF front end or similar systems Competencies Values: Integrity, Accountability, Inclusion, Innovation, Teamwork

Pre/Post Silicon Validation Engineer :- Experience - 4-8 Years Responsibility : Clearly understand the specification and prepare Test Methodology and Test Plan block wise/protocol wise. Implement/Develop tests Block/IP wise as per the features. Identify and implement the System level use cases. Validate the functionality on Platforms(FPGA/Palladium/Silicon) and Publish the results. Report and track the issues until closed with proper resolution and able to communicate the issues effectively across all internal groups. Support cross functional teams for bringup. Identify and Automate the Tests for regressions. Identify the risk areas and be prepared for them before silicon arrival. Document the test procedure and generate the final Silicon/Validation report Skills Required: Strong in Programming Languages: C/C++ and Assembly and Scripting Language: Perl/Python. Debug of diagnostics on various platforms using JTAG, Logic Analyzers, Oscilloscopes. Have hands on experience of SOC architecture, micro-processor verification, and silicon debug environments. Familiar with Lab Equipment(Oscilloscope, Power supplies, Multimeters.. etc ) Database Management tools: GIT, Perforce and SVN High Speed Protocols(any of):USB, PCIe, MIPI, HDMI. Memory Protocols: DDR, SD, eMMC, Flash. Communication protocols: UART, I2C, SPI, CAN, Ethernet etc., Processor Knowledge(any of): IBM, MIPS, ARM, ARC. Expertise in understanding Board Schematics. Strong Problem solving and Debugging skills . Excellent Communication skills. Eligibility : B.E/B.Tech in Electronics/Electrical Engineering, Computer science 4 to 8 years of relevant experience Experience in DDR4 prepare Test Methodology and Test Plan block wise/protocol wise Strong in Programming Languages: C/C++ and Assembly and Scripting Language: Perl/Python Debug of diagnostics on various platforms using JTAG, Oscilloscopes Communication protocols: UART, I2C, Processor Knowledge(any of): IBM, MIPS, ARM, ARC

As an RTL Design Engineer at Nsemi, you will play a pivotal role in developing high-performance digital circuits through Register Transfer Level (RTL) design. Your responsibilities will include designing, modeling, and verifying RTL code using VHDL or Verilog to create efficient and reliable digital systems. You will collaborate with cross-functional teams to ensure that your designs meet stringent performance, power, and area specifications. This role requires a strong understanding of digital logic, excellent problem-solving skills, and a commitment to quality and innovation. Qualification Required: Typically requires minimum of 3+ years of experience in System Verilog, UVM. Bachelors OR Master s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities: As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches. If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality. You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews. Required Technical And Professional Expertise: Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. Understanding of verification tools like Simulator, Synthesis etc. Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. Excellent written and verbal interpersonal skills Self-motivated and great teammate

As an ASIC Design Verification Engineer at Nsemi, you will play a crucial role in ensuring the functionality and reliability of our cutting-edge ASIC designs. You will utilize advanced verification methodologies, including UVM and SystemVerilog, to develop comprehensive test plans, create and execute testbenches, and identify and resolve potential issues. Your work will be pivotal in validating complex designs and ensuring they meet the highest standards of performance and quality. If you have a passion for functional verification and a keen eye for detail, this role offers an exciting opportunity to contribute to groundbreaking semiconductor projects. Qualification Required: Typically requires minimum of 3+ years of experience in System Verilog, UVM. Bachelors OR Master s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities: As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches. If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality. You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews. Required Technical And Professional Expertise: Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. Understanding of verification tools like Simulator, Synthesis etc. Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. Excellent written and verbal interpersonal skills Self-motivated and great teammate