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RTL Design Verification IP Level

1 - 4 years

5 - 15 Lacs

Posted:11 hours ago| Platform: Naukri logo

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Job Description

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage.

Required Candidate profile

Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

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