20 Coverage Closure Jobs

This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products. Your Role Key responsibilities in your new role: This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products. Architect and develop test benches and environments. You will create, simulate, and debug test scenarios, and lead regressions and issue tracking. There will be collaboration with design and systems engineering teams to review specifications and architecture,extract features, and define verification plans. You'll drive coverage analysis and closure, and colla...

Job Description: You will be responsible for performing ASIC/IP/Sub-System/SoC level design verification for high-speed interfaces, ensuring functional correctness across PCIE and other protocols under PVT conditions. Your role will involve developing and executing test plans using SystemVerilog and UVM, as well as collaborating with cross-functional teams for design bring-up, debug, and coverage closure. Key Responsibilities: - Perform ASIC/IP/Sub-System/SoC level design verification for high-speed interfaces - Ensure functional correctness across PCIE and other protocols under PVT conditions - Develop and execute test plans using SystemVerilog and UVM - Collaborate with cross-functional te...

As an ASIC Verification Expert at Sandisk, you will play a crucial role in ensuring the quality and performance of cutting-edge solutions. Your responsibilities will include: - Demonstrating expertise in ASIC verification, System Verilog, UVM, and Verilog. - Leading a team of 2-5 engineers as a technical lead. - Handling IP level verification, testbench architecture development, and Testbench component developments effectively. - Utilizing your expertise in coverage closure, code coverage, functional coverage, and Gate level simulations. - Independently defining verification plans, creating testbenches, test cases, and gate level simulations. - Applying knowledge of serial protocols such as ...

Job Description 8+ years of hands-on ASIC DFT experience with multiple production tapeouts owning full-chip DFT. Proven ownership of MBIST architecture and hands-on insertion across large memory arrays; experience with repair, redundancy, and BIRA/BISR flows. Hands-on scan insertion and compression, ATPG pattern generation and coverage closure. Solid understanding of test-mode timing, constraints, and PnR interactions; experience with test clocks/reset distribution and power intent in test modes. Proficiency with at least one major DFT tool suite : Synopsys (DFTMAX/SpyGlass-DFT/TetraMAX), Siemens Tessent (Scan/MBIST/ATPG), or Cadence Modus. Experience with JTAG/boundary scan and, ideally, IE...

Job Details Job Description: Job Description Lead/manage a team of design verification engineers responsible for IP and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validati...

Hi All, ACL Digital is hiring Design Verification Engineers Experience: 8+ years Location: Hyderabad / Bangalore Join: Immediate Key Skills: 8+ Years in IP/Sub-System/SoC DV Testbench Development Strong in SV UVM, Functional & Formal Verification Hands-on with RISC-V / CPU / PCIe / DDR / Ethernet SoC Integration, Debugging & Coverage Closure Expertise in Assertions & Complex Verification Flows Thanks, K Himabindu

JD : Verification of Debug Subsystem Requirement: 6 years exp Job Profile & Expertise Requirements: End to end Debug Subsystem verification Expertise in RTL DV, GLS, Coverage closure Understanding of ARM Coresight Debug Architecture Work with architecture and SW teams for debug system requirements, Define VPlan ARM-based CPU debug system understanding - trace, crash debug CPU knowledge and expertise in C Strong SV, UVM knowledge

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: The Core design and verification team is responsible ...

You have an exciting opportunity with Tessolve Semiconductor in Bangalore for the roles of RTL Design Engineer and Design Verification Engineer. For the position of RTL ASIC Engineer, you should have at least 7 years of work experience in ASIC/IP Design with expertise in Logic design and RTL design. Your responsibilities will involve IP design and integration, along with proficiency in tools such as Lint and CDC for ASIC development. Knowledge of Synthesis and understanding of timing concepts would be advantageous. Additionally, familiarity with AMBA protocols like AXI, AHB, APB, and SoC clocking/reset architecture is preferred. As a Design Verification Engineer, you are required to have 5 t...

The job is based in Bangalore/Hyderabad and requires a notice period of 15 to 30 Days with a minimum experience of 4 Years. As a candidate, your key responsibilities will include developing test plans, coding and bringing up asm, c++ tests, coding and maintaining UVM test bench components, debugging regression fails, and working with protocols such as DDR, PCIE, USB, MIPI, and PCIE. The ideal candidate should have experience working on Processor based Systems or Sub-system level verification. It is preferred that you have hands-on experience with assembly, UVM, SV, C++, and have worked on developing complex test bench/models in UVM, Verilog, and System Verilog. Additionally, you should have ...

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP. Knowledge of one or more of pro...

Job Description Responsible for developing detailed Technical SoC verification execution plans Writing software driven testcases in C Regression Coverage Closure XPROP, Requirement Traceability Gate Level Simulation at SoC Level PICe, UCle, Ethernet, UFS, USB related experience required. Show more Show less

PR Associate- Corporate Segment Key Responsibilities: - Develop PR Strategies: Create and implement comprehensive PR strategies that align with the brand's goals, ensuring clear communication with our target audience. - Media Relations: Establish, build, and maintain strong relationships with key media contacts, influencers, and industry stakeholders to generate meaningful media coverage and opportunities. - Media Engagement: Manage media inquiries, coordinate interviews with company spokespersons, and pitch proactive stories to relevant media outlets. - Event Management: Organize, manage, and attend press events, product launches, media tours, and other related PR activities, ensuring a sea...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Candidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads. Necessary skills/experience: 1+ years of experience in RTL design verification using SystemVerilog/UVM and industry-stand...

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

Are you a highly skilled Formal Verification Engineer looking to make a significant impact across the entire product lifecycle Join Analog Devices in a senior role where you'll drive the formal verification of complex digital designs, from concept through to release. You'll collaborate with a wide technical community, gaining exposure to diverse technologies and products, all while building a promising career. Job Responsibilities: Formal Verification Planning and Execution: Develop and execute comprehensive formal verification plans for complex digital designs, including both block-level and system-level components. Define precise verification goals, metrics, and coverage targets to ensure ...

Own and develop UVM-based testbench environments for IP/SoC verification Design verification architecture, testplans, and SVA based on protocol specifications (PCIe, CXL, UCIe, AXI, etc.) Drive all aspects of the verification lifecycle including testbench creation, coverage closure, and debugging Collaborate with RTL design teams to resolve issues and close functional coverage Conduct peer reviews to maintain high testbench code quality Contribute technical papers and patent ideas on testbench innovations and verification methodologies Work closely with global teams and ensure timely project execution The Impact You Will Have: Deliver reliable and robust verification solutions that ensure hi...

BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI, APB, AHB) etc Good knowledge of System Verilog Hands-on experience with coverage closure and writing SVA for IP/SOC Good simulation debugging skills Experience with Perforce or similar revision control environment Experience with Python/TCL or any scripting knowledge is an added advantage Job Responsibilities include - Understand Standard Specifications, create testplan ...

Responsibilities: Manage territory sales performance Close deals through effective negotiation Develop new business opportunities Maintain customer relationships Meet revenue targets

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. Knowledge of one or more of...