8 Coverage Closure Jobs

PR Associate- Corporate Segment Key Responsibilities: - Develop PR Strategies: Create and implement comprehensive PR strategies that align with the brand's goals, ensuring clear communication with our target audience. - Media Relations: Establish, build, and maintain strong relationships with key media contacts, influencers, and industry stakeholders to generate meaningful media coverage and opportunities. - Media Engagement: Manage media inquiries, coordinate interviews with company spokespersons, and pitch proactive stories to relevant media outlets. - Event Management: Organize, manage, and attend press events, product launches, media tours, and other related PR activities, ensuring a seamless execution and maximum exposure for the brand. - Media Monitoring & Reporting: Track and analyze media coverage, preparing regular reports on PR activities, performance metrics, and overall impact. - Collaboration with Marketing: Work closely with the marketing team to ensure brand messaging is consistent across all platforms and campaigns. - Industry Awareness: Stay updated on industry trends, competitor activities, and identify potential PR opportunities to maintain a competitive edge. Qualifications & Experience: - Proven experience in corporate segment of PR, with a strong understanding of the industry landscape. - Exceptional writing, communication, and organizational skills. - A well-established network of media contacts and industry professionals. - Strong project management skills, with experience in managing multiple PR campaigns simultaneously. - Ability to work under pressure, manage crises, and provide strategic responses swiftly. Job location: Worli Days: Monday to Friday (In office) Hours : 9:30 - 6:30pm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Candidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads. Necessary skills/experience: 1+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory) Experience in power aware simulation is a big plus Experience on camera verification is a big plus Expertise in Coverage closure , RTL debug skills Expertize in SV – UVM, Assertions based verification, DPI Familiarity in Firmware/emulation (exVeloce) based verification , GLS Familiarity with bus protocols like AHB, AXI, ARM based system architecture Experience with Perl, Python, or similar scripting language Excellent problem solving skills & Verification aptitude Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

Are you a highly skilled Formal Verification Engineer looking to make a significant impact across the entire product lifecycle Join Analog Devices in a senior role where you'll drive the formal verification of complex digital designs, from concept through to release. You'll collaborate with a wide technical community, gaining exposure to diverse technologies and products, all while building a promising career. Job Responsibilities: Formal Verification Planning and Execution: Develop and execute comprehensive formal verification plans for complex digital designs, including both block-level and system-level components. Define precise verification goals, metrics, and coverage targets to ensure exhaustive validation of design functionality. Model Development and Property Writing: Create robust formal models and assertions using industry-standard formal verification tools and techniques. Write and debug properties, constraints, and assumptions to rigorously verify design intent and proactively identify corner-case issues. Debugging and Issue Resolution: Analyze counterexamples and debug failures to pinpoint the root causes of design issues. Work closely with design and RTL teams to efficiently resolve issues and ensure complete alignment with design specifications. Tool and Methodology Expertise: Utilize advanced formal verification tools such as JasperGold, Questa Formal, or equivalent, to perform exhaustive verification. Stay updated on the latest advancements in formal verification methodologies and tools, actively driving their adoption and continuous improvement within the team. Collaboration and Communication: Collaborate effectively with architects, designers, and validation engineers to deeply understand design requirements and constraints. Documentation and Reporting: Document formal verification strategies, methodologies, and results for future reference and auditability. Generate detailed reports summarizing verification coverage, key findings, and actionable recommendations. Position Requirements: Bachelor's or Master's degree in Electrical/Electronics/VLSI with 4-6 years of relevant experience. Demonstrated experience with Formal tools such as Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal, with prior implementation experience on SoCs, CPUs, GPUs, or other high-performance computing devices. Proficiency in writing SystemVerilog Assertions (SVA) or Property Specification Language (PSL). Solid understanding of digital design concepts, RTL design, and hardware description languages (Verilog, SystemVerilog, VHDL). Strong analytical and debugging skills to effectively identify and resolve complex design issues. Ability to analyze counterexamples and provide actionable feedback to design teams. Excellent communication and interpersonal skills to work effectively in a collaborative team environment. Familiarity with scripting languages (Perl, Python, TCL) for automation. Experience in common communication protocols such as ARM AMBA, I2C, SPI, UART is preferred.

Own and develop UVM-based testbench environments for IP/SoC verification Design verification architecture, testplans, and SVA based on protocol specifications (PCIe, CXL, UCIe, AXI, etc.) Drive all aspects of the verification lifecycle including testbench creation, coverage closure, and debugging Collaborate with RTL design teams to resolve issues and close functional coverage Conduct peer reviews to maintain high testbench code quality Contribute technical papers and patent ideas on testbench innovations and verification methodologies Work closely with global teams and ensure timely project execution The Impact You Will Have: Deliver reliable and robust verification solutions that ensure high-quality IP/SoC design Influence UVM testbench architecture through innovation and best practices Improve efficiency and accuracy in verification through SVA and advanced debugging Enable faster time-to-market by streamlining simulation and debug processes Contribute to Synopsys IP leadership by ensuring verification excellence across global projects What You'll Need: 48 years of experience in UVM-based verification for IP/SoC Strong SystemVerilog knowledge and protocol understanding (PCIe, CXL, UCIe, AXI, etc.) Hands-on experience with functional coverage closure and SystemVerilog Assertions (SVA) Proficiency in simulation tools and waveform debug tools like DVE/Verdi Familiarity with version control tools (e.g., Perforce) Scripting knowledge (Python, TCL) is an added advantage Strong communication, problem-solving skills, and ability to work across teams and geographies

BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI, APB, AHB) etc Good knowledge of System Verilog Hands-on experience with coverage closure and writing SVA for IP/SOC Good simulation debugging skills Experience with Perforce or similar revision control environment Experience with Python/TCL or any scripting knowledge is an added advantage Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification Be single point of contact with hands-on experience on all verification tasks Testbench Creation Testplan creation Coverage closure SVA Release Perform peer review of testbench code for continuous quality Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide Lead team of engineers to perform various verification activities on IPs/Subsystems Anticipate problems and risks and work towards a resolution and risk mitigation plan Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments Review various results and reports to provide continuous feedback to the team and improve quality of deliverables Report status to management and provide suggestions to resolve any issues that may impact execution The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative

Responsibilities: Manage territory sales performance Close deals through effective negotiation Develop new business opportunities Maintain customer relationships Meet revenue targets

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. Periodically publish technical papers and/or file patents on the feature updates/innovation carried out. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.