665 Pcie Jobs - Page 15

Experience in the PCB design process: schematic capture, layout, generation of design files, BOMs, and release. Worked with schematic capture tools like OrCAD & Allegro PCB. Hardware design, system/product level experience, Project Management. Product architecture experience based on different SoC. Experience In hardware/product development, integration, testing, compliance & support Project monitoring, controls & Delivery. Team Handling & Team Mentoring Proposal & RFQ handling, BOM costing & optimization. Digital, Analog, Mixed Signal Design Experience for consumer/industrial/medical markets ARM / Microcontroller Experience. Experience in High speed design like DDRx, PCIe, MIPI, LVDS interfaces Audio and Video Design Experience - Cameras, LCD, HDMI, NTSC/CVBS Test and Debug - Board Bring Up, Interface testing Instrument Knowledge - CROs, Logic Analysers, Spectrum Analyser, CMW500, protocol analyser. Experience in Multi-layer PCB Layout design approach & design reviews, SI knowledge. Exposure to design tools - ORCAD, Allegro. Customer communication and front ending for technical aspects. Design analysis for SI, PDN, Thermal, EMI/EMC. Product qualification / Compliances test experiences Experience in quality product release to customers.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Lead Engineer Location: Mysore Work Type: Onsite Job Type: Full time Job Description: Should be able to build test plan, tests, coverage assertions from Specification. Architect and build testbench and testbench components. Good in UVM,SV,C SVA. Familiar with industry protocols, such as AXI, APB, AHB, PCIe, SoC. Very good in debugging. Worked with industry standard EDA tools Synopsys, Cadance simulators and debugging tools. Good to Have Skills: Experience with scripting and automation. Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS and a proactive approach to automation. Exposure to SOC verification, Formal verification methodologies. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Role: SoC NoC Verification Lead Location: Bangalore Job Type: Full Time Work mode: Onsite - 5 days WFO 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using System Verilog/UVM. Good in verifying the communication between the CPU subsystem and the NoC (instruction/data/caches) not just general NoC trafficor peripheral interfaces. Working with cache, MMU, interrupt systems is also important. Cache coherency protocol testing Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage test bench architecture and automation frameworks.

Job Overview: As a Test and Validation Engineer at TE Connectivity, you will play a crucial role in the design, verification, and validation testing of high-speed products within cable assemblies, targeting data centers and wireless infrastructure. This position requires you to work independently on validation projects and test system design, including hardware selection and programming . You will collaborate closely with a cross-functional team, including electrical, mechanical, manufacturing, and operations engineers, to bring innovative product designs to life. Your primary responsibility will be to oversee the electrical validation of products and platforms, from initial analysis through production verification and manufacturing . You will address complex design challenges and leverage advanced hardware and software tools to ensure successful product development. Responsibilities: Develop and validate high-speed test systems and manage validation activities throughout the product development cycle. Establish testing requirements for new products based on electrical and software specifications. Design and implement high-speed cable test systems/fixtures from conception to manufacturing deployment. Create and validate test system architecture, including system diagramming, software development, hardware build, and product validation. Generate actionable recommendations based on design reviews and product specifications. Make data-driven decisions regarding product functionality and identify areas for improvement. Required Skills/Experience: Bachelors degree in electrical/electronic engineering, masters degree preferred. Experience with high-speed test equipment ( e.g., Digital Sampling Oscilloscope, Vector Network Analyzer, Bit Error Rate Tester, TDR, Pattern Generators, Power Supplies ). Proficiency in both manual and automated testing. Familiarity with hardware environments. Familiar with Python programming/LabView Familiarity with GIT, Bitbucket, JIRA, and CI/CD pipelines. Strong analytical skills to interpret test and lab data, identify issues, and develop solutions. Excellent verbal and written communication skills. Ability to work effectively in a global environment, accommodating varying time zones, and collaborating across geographies. Fluency in English (verbal and written) is required. Highly motivated, quick learner, and capable of working independently. Nice to have Skills/Experience: Familiarity with embedded systems and ANSI C Familiarity with signal conditioning techniques (equalization, amplification, FIR’s, CTLE’s) J miliarity with PAM4/8 and other higher-order modulation techniquesJ

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructuregroup is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. We are looking for experienced passion driven SW engineers to join our R&D team. Stellar programming skills in one or more C, C++, golang, Shell scripting, Python. Some work experience in software development on embedded/Linux platforms is preferable, but we are open for you as long as your programming skills are right up there. Quick learner of software architecture and module design. Capacity to connect the dots in complex legacy code while developing new features. Understanding on some of the below topics is valuable as these skills will be directly usable. L1 application SW area Software system design, inter-process communication, threading and other OS concepts. Device driver area Boot process on X86 processors with multi OS support, uboot, coreboot. Some experience with BSPs and board provisioning/bring-up. PCI, PCIe, SPI, DMA and I2c protocols. BCM switch programming. IP Stack drivers working knowledge, io-pkt driver. Experience from automated testing in SW development environment We have the opportunity for you to become a systems engineer in the Embedded space and much more. Develop and own L1 application(control path and data-path), related device driver software and features working closely with requirements and customer account teams with deep customer focus. Understand, drive and develop system wide impact features from architecture, design to delivery.Team is also responsible for designing E2E solutions for communications frameworks and data-path setups spanning across Digital (packet) and Optical (channels) areas. We adopt smart and latest technologies to ensure we keep pace with the technology world devising efficient solutions. We have complete ownership and hence responsibility on how a solution is to be devised and implemented. It could be home grown or from 3rdparty application pulls finally ending up in customizing these to suite our customers needs. We go the way to facing and resolving customer queries and resolving customer issues being directly involved with the customer live issues. The team takes full responsibility that a new feature is delivered on time with the right quality using state-of-the-art continuous integration pipelines. We strive for fully automated test suites following TDD.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash... Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE Other Languages EnglishB2 Upper Intermediate Seniority Regular

Project description The team is responsible for development, quality assurance and delivery of all kernels (KMDF) and user (UMDF) level drivers for RAID UEFI, Windows and Linux drivers for the laptops, desktops and workstations that support the RAID solution. As a software engineer in this team, you will work on hardware and software. We are a vertically integrated team spanning from firmware development right up to application layer. As a part of this world class team, you will get an exposure to the fascinating world of RAID. In this role, you will be actively participating in research, concept development and design ideation to create world class software and firmware. Responsibilities Candidate's primary responsibility is developing Windows Drivers for AMD x86 platform products. Candidate will have backup responsibilities of developing Linux Drivers, Application/tools development. Sustain the design, development, integration, testing and deployment of AMD windows solution. Includes cross cultural communication with vendor and customer. Skills Must have Preferably relevant experience of 4 8 years. Advanced programming skills in C/C++ for operating system kernel & systems development Solid understanding and experience with the Windows Network or Storage Driver architecture, WDF & WDM. Good understanding of PCIe, I2C , UFS, NVMe protocols. Good working knowledge of Storport and NDIS miniport driver. Deep Knowledge of Computer Architecture and Windows Kernel Internals. Good understanding of operating systems concepts, data structures, x86-64 architecture. Proficient use of git Python, Shell Scripting, BIOS knowledge an added advantage Ability to work with minimal supervision on more than one task in parallel. Ability to mentor technically and must be a self-starter. Good communication and time management skills Working with geographical teams an added advantage Nice to have Bachelors/master's in engineering. Other Languages EnglishB2 Upper Intermediate Seniority Regular

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: ASIC Design. Experience5-8 Years.

Description & Requirements Position Responsibilities: Work cross-functionally across design, hardware, software, test, life cycle engineering & support Design, develop & port firmware for motorized fastening systems in C, C++ on RTOS Work closely with motor control experts to implement programmable fastening strategies and behaviors through software algorithms Qualifications Knowledge, Skills and Abilities: Must have: embedded systems programming C/ C++ on RTOS Multithreaded programming Programming data transfer over SPI, UART, PCIe Integration, debugging skills Nice to have: Basic knowledge of dc motor control for speed and torque Experience: Must have: 10+ years of experience as a software development engineer 5+ years of experience in all the embedded systems programming areas listed above Nice to have: Experience with motor control electronics and software for any product

SOC Engineering, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 8604 Remote Eligible No Date Posted 16/06/2025 Job Description and Requirements: At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world s most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you. Job Description and Requirements The role is for SoC Verification in the System Solutions Group (SSG). The role primarily requires implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification and physical implementation expertise to enable leading edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SOCs for high-performance computing, automotive, aerospace & defense, and more. Responsibilities Understand the design specification, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyse system Verilog assertion and coverage (code, toggle, functional). Work alongside other members of the verification team to analyse, develop and execute verification test cases and able to provide relevant solution to issue. Work as a lead, mentor young engineers and help them in debugging complex problems. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. Ramp-up on new Verification tools and methodologies using Synopsys Products to enable customers. Develop innovative solutions to problems with little guidance and implements them independently. Set task-level goals and consistently meets schedules. Work with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions. Required B.E/B. Tech/M. E/M. Tech in electronics with 4-8 years of experience in verification domain. Prior work experience on IP level or Soc level (Preferred) verification is must. Good understanding of processor based Soc level verification which includes native, Verilog ,system Verilog and UVM mix environment is desirable. Hand on experience with verification tools such as VCS, waveform analyzer and third-party VIP integration (such as Synopsys VIPs) is must. Hands on experience in UVM. C/C++, System Verilog verification language. Good understanding of AXI-AMBA protocol variants is desirable. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving, analytical and debugging skill is must. Prior work on ARM core verification is desirable. Prior work on USB, PCIe, MIPI Protocols is desirable. Good communication skills. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Expertise in the x86 BIOS / UEFI FSP / coreboot development. Expertise with x86 CPU/APU architectures and associated compilation tools. Expertise in C programming. Expertise with platform bring-up. Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM. Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms.. Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow. Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc. Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required. Good coreboot upstreaming exposure. Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff. Understanding of coreboot & FSP build tools and build processes. Good understanding of UEFI framework concepts to port UEFI code to FSP. Working knowledge of Git for code reviews, source code management, and BIOS releases to QA.. Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements.. Good understanding of x86-64 architecture from BIOS developer's perspective.. Good understanding of UEFI BIOS Boot flow.. Basic understanding of Linux Kernel like software development concepts (Kconfig).. Location-Delhi NCR,Bangalore,Chennai,Pune,Kolkata,Ahmedabad,Mumbai,Hyderabad

Linux developers with hands-on experience developing Linux device drivers of 3 to 8 years. Working knowledge of any of the peripheral Linux drivers areas such as: USB, PCIe, HSIC, etc., DWC, USB Gadget drivers, Android USB drivers, USB host controller drivers. DMA client/controller driver development experience Experience in PCIe debug using Lecroy PCIe analyzer. Very good C programming and Linux skills. Good understanding of Linux OS concepts and Linux Kernel internals. Good system debugging skills and root cause analysis. Candidates should be familiar in understanding the peripheral hardware, Device Data sheets, Schematics, Specification and Reference manual. Some experience with Qualcomm chipset code, drivers, tools usage and system design. Preferably good understanding about ARM32/64 chipset architecture. Domain:- Boot-loader, Linux BSP, Device driver for PCIe, USB, etc JOB Description for Windows Drivers: Advanced programming skills in C/C++ for operating system kernel & systems development Solid understanding and experience with the Windows Network or Storage Driver architecture, WDF & WDM. Good understanding of PCIe, I2C , UFS, NVMe protocols. Good working knowledge of Storport and NDIS miniport driver. Deep Knowledge of Computer Architecture and Windows Kernel Internals. Good understanding of operating systems concepts, data structures, x86-64 architecture. Proficient use of git Python, Shell Scripting, BIOS knowledge an added advantage

Mandatory Skills : 5-15 years of experience in the x86 BIOS/UEFI FSP/coreboot development Experience with x86 CPU/APU architectures and associated compilation tools Expert in C language Experience with platform bring-up Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff Working experience of industry standard protocols like PCIe, SPI, eSPI, ACPI, SMM Experience on working with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. Experience on working with Intel FSP package source code and understanding of coreboot & FSP boot flow Understanding of coreboot & FSP build tools and build processes Experience of working with different coreboot payloads like edk2, SeaBios, Tianocore etc Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required Good understanding of UEFI framework concepts to port UEFI code to FSP Additional Skillset : Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. Good understanding of x86-64 architecture from BIOS developers perspective. Good understanding of UEFI BIOS Boot flow. Basic understanding of Linux Kernel like software development concepts (Kconfig). We are seeking a talented and motivated Software Engineer to work on Vulkan/OpenGL/OpenCL libraries. As a key member of the graphics team, you will work on challenging and groundbreaking projects in the open-source domain and you will have the opportunity to collaborate with leading experts and contribute to the development of cutting-edge graphics technology. Responsibilities Develop high-performance, visually stunning graphics applications using OpenGL/Vulkan/OpenCL APIs. Troubleshoot and resolve complex graphics-related issues. Development of C++ based automotive applications. Conceptualization, prototyping, design, development & unit testing of application SW based on product requirement. Collaborate with cross-functional teams to implement innovative graphics solutions. Working with the extended team (developers & verification team) to enhance the application & functionality. Participate in debugging and troubleshooting to identify and address software (build, algorithm/ functionality/ dependency) issues. Required skills The ideal candidate possesses a strong foundation in C/C++, a deep understanding of OS concepts. Experience in integrating OpenGL/Vulkan/OpenCL to Graphics Processing Unit. Expertise in at least one graphics API (OpenGLES, Vulkan, or OpenCL) OR extensive experience for graphics development. GPU optimization experience. Add on: Past experience with Mesa 3D Graphics library.

Mirafra Technologies is looking for experienced Design Verification Engineers to join our dynamic team in Hyderabad/Bangalore If you're passionate about digital design and verification and want to work on cutting-edge SoC projects, this is the opportunity for you! Key Responsibilities: Develop and execute test plans and testbenches using SystemVerilog/UVM Perform functional and code coverage analysis Debug RTL and testbench issues efficiently Collaborate with design and architecture teams to ensure verification completeness Required Skills: Strong coding skills in Verilog Hands-on experience with SystemVerilog and UVM-based verification Experience in SoC/IP level verification Good understanding of design verification methodologies , assertions, and coverage Familiarity with debugging tools , simulation , and scripting (Python/Tcl/Perl) Preferred Skills: Exposure to high-speed protocols (PCIe, USB, Ethernet) Knowledge of formal verification or power-aware verification is a plus Why Join Mirafra? Work with global semiconductor leaders, gain deep technical exposure, and be part of a growing and collaborative team. Apply Now by sending your resume to swarnamanjari@mirafra.com

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for IP/SoC level verification. Develop test benches from scratch, including creating drivers, monitors, and predictors. Utilize System Verilog to write verification code and debug issues. Collaborate with cross-functional teams to identify requirements and develop test plans. Participate in peer reviews to ensure high-quality deliverables. Desired Candidate Profile 4-10 years of experience in SOC/IP Verification with expertise in DV on Cpu, DDR, Ethernet, PCIe protocols. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of GLS (Global Logic Synthesis) concepts.

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for PCIe, DDR, Ethernet interfaces on SOCs. Develop test benches in System Verilog for verifying complex digital designs. Collaborate with cross-functional teams to identify requirements and develop test plans. Utilize GLS (Golden Labs Simulation) tools for simulation setup and debugging. Participate in peer reviews to ensure high-quality deliverables. Must have good debugging skills. Experience in any of the slow speed peripherals like I2C, SPI, UART is a plus. Desired Candidate Profile 5 years of experience in SV/UVM Lead role with expertise in design verification using UVM methodology. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of SystemVerilog programming language and its application in DV testing.

FPGA design engineer will take part in the design domains of signal processing and data processing, image processing, other high-speed and control applications, implementing these functions on high-density state of the art FPGAs. Work may include specifying, architecture/microarchitecture definition and hands-on implementation work for every aspect of FPGA design, working closely with the system, software, and FPGA design and verification, guide and mentor juniors in the areas and Delivery of expert level technical support in the resolution of FPGA application issues at programming level. In addition to the FPGA implementation, the engineers are expected to understand subsystem/algorithm level behaviour of such designs and be able infer the necessary hardware design/resources necessary for a given subsystem level specification. Work may involve HDL level coding/verification/testing and/or System C coding levels and taking ownership of all aspects of the design verification of the FPGA chips and/or its functional blocks. Examples of possible micro streams of work: CCD/CMOS Image array readout at high speeds Formatting such data and serial or parallel transmission of the same to other subsystems Implementation of complex image or signal processing algorithms Implementation of i/o rich control functions to interface a large number of subsystems to central controllers. Working closely with microcontroller programmers, instantiation of controllers with sequential code inside FPGAs etc mapping algorithms and standards (PCIe, NVMe, SATA,USB, Ethernet, TCP/IP, TCP/IP off load engine (TOE), SERDES, LVDS, and Memory Controllers DDR2/DDR3 ) to hardware and architecture/system design trade-offs standard bus protocols, including I2C, SPI, USB, PCIe. Candidates should preferably have good quantitative aptitude and understand analy Content coding like Verilog/VHDL, or System C or equivalent, exposure to complex/high density FPGAs and FPGA-SoCs Familiarity with Matlab and Simulink Vitis Unified Software Platform - Xilinx or similar Bachelors in Electronics or equivalent stream and a minimum of 10 years experience or Masters Degree in a related specialization with a minimum of 8 years experience in Electronics Design/Embedded Electronics, out of which the most recent 6 years must have been in state of the art high density FPGA environments. FPGA Design Engineer Azista BST Aerospace Plot No. 16, Sanand Land Industrial Estate Corporation, Sarkhej-Sanand Road, Ularia, Sanand, Ahmedabad, Gujarat, India - 382 210. Registered Office Sy.No 80-84, Melange Towers, 4th Floor, C Wing, Patrika Nagar, Madhapur, Hyderabad, Telangana, India - 500 081.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 5+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (16+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver