458 Pcie Jobs - Page 17

Responsibilities -Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills at kernel and user space and exposure to different debugging tools Knowledge on PCIe, Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Skills Must have Candidate should have 5-8yrs experience Proficient in C and embedded systems. Experience in Linux driver development (PCIe/USB/Ethernet) and application development. PCIe driver development experience. DMA client/controller driver development experience Hands-on experience with Configuration Management tool like GIT, Perforce. Have an interest to constantly learn and share new findings. A quality mindset, ability for strategic thinking and a drive to always improve. Self-motivated Nice to have B.tech/M.Tech in CSE/IT/ECE/EEE/EI Other Languages English: B2 Upper Intermediate Seniority Regular Refer a Friend Positive work environments and stellar reputations attract and retain top talent. Find out why Luxoft stands apart from the rest. Recommend a friend Related jobs View all vacancies Senior UEFI/BIOS Developer C Embedded India Bengaluru Regular C Embedded / C++ Software Engineer C Embedded Poland Remote Poland Regular C Embedded / C++ Software Engineer C Embedded Turkiye Remote Turkey Hyderabad, IN, India Req. VR-112290 C Embedded Automotive Industry 03/03/2025 Req. VR-112290 Apply for Senior Software Engineer - PCIe Driver Development in Hyderabad, IN *

Who We Are Arista Networks is developing cutting-edge network solutions to address the scalability, performance, and reliability requirements of large-scale high-performance computing and cloud data centers. Our team consists of experienced management and industry- leading engineering talent. Arista offers great benefits, work-life balance, and an environment that will challenge you to make a name for yourself in this industry. Look to join us as a premier company developing a new class of integrated network solutions for the next generation high-performance computing and web data centers. About the Role Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experie

Who We Are Arista Networks is developing cutting-edge network solutions to address the scalability, performance, and reliability requirements of large-scale high-performance computing and cloud data centers. Our team consists of experienced management and industry- leading engineering talent. Arista offers great benefits, work-life balance, and an environment that will challenge you to make a name for yourself in this industry. Look to join us as a premier company developing a new class of integrated network solutions for the next generation high-performance computing and web data centers. About the Role Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experie

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ years of experience in Design Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.

About The Role : As SoC/System Debug specialist, the candidate will be part of a top-notch debug team for Intel post silicon server validation. Manual debug team will be gate keeper to ensure a healthy product quality release to internal and external customers. Responsibilities include systematic debug of complex failures at system level, designing the experiments to root cause the issues, co-ordinate with different teams for execution of experiments. Once the issue is root caused, work with design teams on work around and fix validation. The position will support various levels of experience with following qualifications. Works with architecture and design teams to implement different DFD methodologies and necessary hooks into SoC designs. This position will also mentor and coach other team members to develop necessary expertise and skills. Qualifications Bachelor's/Master's in Hardware Engineering or Electrical/Electronics Engineering or Computer Engineering or Computer Science with 10+ years of related work experience. Candidate must have high degree of hardware architecture/ microarchitecture experience in CPU/SoC/Chipset and a few of the subsystems/areas given below Strong knowledge and skills of Intel IA (IA32 architecture with uArch debug knowledge of Intel's Core and Uncore or equivalent architecture.) Passionate about working on CPU hardware and enjoys various levels of debugging Good data analysis skills and attention to details, Patient and disciplined problem-solving skills Expertise in CPU bring up, system level debug, root cause isolation, debug methodology and tools Knowledge of SOC level flows and deep understanding of some of the domains - CPU core, IOs, Coherency, reset, Power management, virtualization Understands System HW/FW/SW as a whole Excellent failure boundary minimization skills Must possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Optimizes debug process and drives systematic improvements in debug methods, tools and features based on expertise and debug findings. Hands-On experience of complex SoC sightings and exposure to running cross-team/site Task forces Knowledge on Debug Tools for JTAG, on chip trace features and ability to debug via OSC/LAs etc; Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGA's, etc.), usage of different Analysers/exercisers (PCIe etc.) Good working knowledge in C/C++/Python SW programming for content development and scripting Demonstrated collaboration skills working with different partner teams like design, architecture, firmware, tools, manufacturing teams during complex failures debug Excellent written and oral communications and experience working in a cross functional /cross geography team environment are essential Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements. Working Model This role will require an on-site presence. *

Required: Strong C/C++ programming skills, OS and Compiler concepts Hand on experience in setting up reference target boards Hands on experience in low-level Linux kernel and embedded systems development Strong expertise in X86 architecture. Required Candidate profile Understanding of the kernel OOPS, backtrace Deep knowledge of Linux kernel internals (process scheduler, interrupt handling,memory management, concurrency/synchronization,memory allocation )

About Applied Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Your Opportunity As an EE you will be working in highly technical, flexible environment with top level exposure to all cutting-edge technologies and legacy system. You will have the opportunity to engage in the Product Life Cycle from concept designs to volume manufacturing for the modules/systems enabling to solve the High value problems of our customers. You will be offered unique opportunities and challenges to get interfaced with our customers and suppliers. Applied continues to grow and is the #1 Semiconductor Manufacturing Company in the industry. Key Responsibilities Expert level technical support in the resolution of FPGA design and application issues Design or modify electrical/electronic engineering assemblies, layouts/schematics and/or detailed drawings/specifications of moderate scope under general supervision. Create design and specification documents, test plans and progress reports. Conduct obsolescence risk assessment for prompt risk mitigation strategy and implementation to ensure product manufacturability and sustenance. Coordinate the procurement and assembly of electrical/electronic components/equipment and identify sources of critical parts and subsystems to resolve technical issues. Participate in resolving customer complaints & escalations through root-cause analysis and corrective-preventive actions. Functional Knowledge (Required Skills/Experience): Extensive knowledge of RTL design language. Hands on experience on design, simulation and testing of FPGA application. Good knowledge of electrical design engineering, Digital/Analog/Mixed signals, Power electronics, Controls and Instrumentation. Good knowledge of electrical engineering design concepts and applications - components, schematics, electrical system. Good understanding on communication interface such as I2C, SPI, USB, Wi-Fi, IoT and Bluetooth, memory device such as SRAM, DDR3+, and high speed communication protocols such as ETHERCAT, ETHERNET, PCIe Experience on microcontrollers and microprocessor design. Interpersonal Skills Demonstrate strong written, oral, and interpersonal communication skills. Excellent aptitude for multi-tasking and willing to learn. Qualifications Bachelor's Degree in Electrical Engineering / Electronics & Communication

Job Specs : We are seeking a highly skilled and motivated Firmware Software Development Engineer (Power Management) to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of embedded products. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Desired Profile : Engineers with expertise in firmware development related to BIOS, power management and PCIe Expertise in Embedded C programming Strong knowledge of UEFI BIOS, ACPI. AGESA knowledge is a big plus Strong knowledge of platform BIOS development Good knowledge SoC power management CPU / Device power states, hot-plug etc Firmware development & release process understanding Prior experience working with firmware design & development OS / Drivers / Software stack understanding is a plus Excellent communication and articulation skills

Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Preferred Qualifications 5+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Interested can share resume on Shubhanshi@incise.in

What You ll Do The job involves working on Cisco UCS AI Server platform development activities. This team develops Software and Firmware for Cisco UCS platforms. This includes development of Server BMC (a.k.a Cisco Coordinated Management Controller) Firmware, Software, tools and utilities. In this role, you will have the opportunity to work and contribute in technical charter and provide technical development support for Baseboard Management Controller (BMC) activities. You will be part of the UCS AI Rack Server team, Bangalore, which is a key part of Ciscos Data Centre strategy. We are looking for hands-on Technical Engineers as applicants who strive in a fast paced start-up like environment. You will be part of a dedicated team and open communications, empowerment, innovation, collaboration and customer success are the foundations of the team. Responsibilities include: Software Engineer in the AI Server BMC team Demonstrate a high degree of originality and innovation in design/development activities. Be a hands-on Engineer working across different architectures and environments. Work closely with Hardware Team for reading and understanding schematic hardware bring up and debug activities. Work closely with group of other architects/collaborators to define the complete design. Help the Senior team members in the design of interfaces between products to ensure interoperability. Develop software in a real-time Linux (or similar) OS environment for Cisco UCS server platforms. Develop system software to meet the specification of platform requirements. Comprehend newer, complex datacentre customer requirements and translating to engineering features. Who You Are Required Experience and Skills: Excellent Data Centre/Cloud platform engineering Expertise Excellent hands-on experience in Firmware, Device Driver and Embedded/Real time systems development. Good knowledge of x86 and ARM architectures. Very Strong Expertise in C and other programming language(s) expertise is a plus. Very Strong proponent of Design understanding and abreast of new architecture/design/development methodologies Excellent verbal and written skills and professional presentation. Desired Experience and Skills Experience in Server/Storage chassis platform technologies A good experience and background in management controller firmware development (BMC) and IPMI/Redfish. Experience in HW tools like JTAG debuggers, I2C analyzers, Oscilloscopes and flash memory programmers. Experience in Industry standard protocols like PCIe, NVMe, CXL and other Interconnect/Server technologies would be plus. Experience with GIT/Bitbucket 4-8 Years of experience BE/BTech/ME/MTech in Electronics/Computer Science preferred.

Who Youll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Cisco s revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelor s Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Master s Degree in EE or CE with 3+ years of related work experience. Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Architect, Design and Develop Storage solutions on DPUs in the areas of NVMe-PCIe NVMeoF(TCP, RDMA), VirtIO. Build Innovative solutions and solve challenging problems in areas of Storage Disaggregation, Virtualization, Storage services (Encryption, Compression, Replication and Erasure Coding), etc Contributions to Patents, Standards and Open Source Initiatives Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring ups Debug/fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Prior Storage experience in any of NVMe, NVMe-oF, VirtIO, SCSI/FCP, iSCSI, RDMA and TCP areas Strong object-oriented programming background, C/C++ Strong systems programming background Exposure to Linux block layer, block device drivers (linux, ESXi, Windows), QUEM/KVM Virtualization, PCIe, TCP and basic networking is added advantage Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Motivating leader with good interpersonal skills ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Participates in failure analysis and platform debug to root cause failures across platform domain areas like Power Management, Memory, Reset, PCIe, CXL, RAS, Security, Manageability. Defines, develops, and executes platform-based validation environments, test suites, and plans and drives characterization and yield enhancements to ensure testability, manufacturability, and production of integrated circuits. Develops debug methodologies, complex software programs for new device features, and design validation vectors. Evaluates components to ensure performance meets specifications and delivers optimal match of component requirements with production equipment capability. Applies knowledge of platform level tools and techniques to conduct root cause analysis, failure analysis, troubleshoot, and debug cross discipline and complex integration issues of the platform. Documents test results, analyzes test data, communicates results while continually improving test methods. Conducts integrated platform level validation, verifies that the product meets quality and/or reliability attributes and complies with applicable specifications. Drives product requirements as needed by customers to ensure necessary capabilities for platform validation activities. Collaborates with multiple teams across board design, power, platform design, development, and debug to ensure all features are validated and optimized timely. Works with product development engineers and end customers as first points of contact to support debug, root cause analysis, and customer platform issues. Qualifications You must possess the minimum qualifications to be initially considered for this position- Candidate must possess a master's or bachelor's degree in electrical or computer engineering or a related discipline- Experience on Intel architecture and debug, failure analysis is a plus- Good problem solver with good hands-on skills for programming using Python/Unix Shell scripting/C and able to do source code level debug firmware/platform issues and build scripts for automating test content would be an advantage.-Good understanding of Intel Architecture Operating System Drivers, BIOS flows, compute/memory/storage performance design fundamentalsEngineers focus will be to Develop and implement validation strategies, including defining the number of cycles required to meet QRC (Quality, Reliability, and Compliance) criteria. Create new test content and automate testing based on customer use cases to identify and address coverage and interoperability gapsin Reset and PM domain. Provide expert debugging and support for the enablement of various custom features and functionalities. Collaborate with internal teams to ensure feature stability and lead task forces to resolve DPMO and reset issues.Experience must also be inclusive of1. Platform validation and or debug experience with Intel Architecture and Server Platform experience2. Familiarity with debugging tools such as Intel ITP based environments, protocol analyzers, logic analyzers, power meters and DAQs3. Must be willing to engage with external customers when needed4. Experience with Python or Unix Shell script development is an advantage Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : React.js Good to have skills : NA Educational Qualification : 15 Project Role :Application Developer Project Role Description :Design, build and configure applications to meet business process and application requirements. Must have Skills :React.jsGood to Have Skills : Job Requirements :Key Responsibilities :Lead the design development and implementation of highquality applications using Reactjs Collaborate with crossfunctional teams to ensure timely delivery of applications that meet business requirements Provide technical guidance and mentorship to team members ensuring adherence to best practices and standards Identify and mitigate technical risks ensuring the stability and scalability of applications Technical Experience :Professional and Technical Skills Proficiency in Reactjs Strong understanding of Front End Development best practices and standards Professional Attributes :Good Communication skills Educational Qualification:15 Additional Information : Qualification 15

UST Designation: Associate III - Semiconductor Product Validation Requirement name: Python Automation Engineer with Validation Who we are: At UST, we help the world s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30, 000 employees in 25 countries, we build for boundless impact touching billions of lives in the process. Visit us at . The Opportunity : Key Responsibilities: This individual will be primarily responsible for development of system test plan, test cases and respective automation of individual modules / products (compute, accelerators, GPUs) that go in to Data Center or Cloud. Interfacing with silicon, platform hardware, and firmware teams during test content development based on product requirements. Development of Automation for the test content developed and execution of it to make sure product meets the quality criteria and spec adherence and meet project schedules and timelines. Required Skills & Qualifications Key Responsibilities: Python automation - advanced level Embedded knowledge (micro-controller exposure and FW knowledge) OS level (Linux or Windows) debug and triage exposure Any exposure to Server space, ARM, Security, PCIE, UEFI/BIOS, BMC, Hypervisor is a big plus Skills: Python, Automation Testing, Server, PCIE, UEfi What we believe : We re proud to embrace the same values that have shaped UST since the beginning. Since day one, we ve been building enduring relationships and a culture of integrity. And today, its those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do. Humility: We will listen, learn, be empathetic and help selflessly in our interactions with everyone. Humanity: Through business, we will better the lives of those less fortunate than ourselves. Integrity: We honour our commitments and act with responsibility in all our relationships. Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation. All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law. UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance. To support and promote the values of UST. Comply with all Company policies and procedures

About The Role : The main responsibilities of the job includes: Define, develop, and perform functional validation for GPUs in post-silicon environment, focusing on validation of PCIe in the context of discrete GPU. The job requires: Ability to capture analyzer traces and debug, ability to use exerciser for compliance. Ability to debug CV5 compliance issues. Ability to understand high-level spec and correspondingly develop test plan, test content and debug scripts, etc. Driving PO execution and debugs. Familiarity with compliance workshop and ability to debug issues across multiple hosts. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 6+ years of industry experience The years of experience mentioned above must include: PCIe post-silicon validation. Debugging PCIe functional and compliance issues Preferred Qualifications: Experience in driving post-silicon validation as technical lead Experience in GPU post-silicon validation Experience in engaging activities in compliance workshop. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience. Related technical experience should be in/with:Silicon Design and/or Validation/Verification. Preferred Qualifications: Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB, I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Hiring: SoC (System-on-Chip) Architect / MCU (Microcontrollers) Architect Location: Noida & Hyderabad Experience: 10-25 years Work Mode: Hybrid (3 days in office) We are seeking an experienced SoC or MCU architect to join our team. This role presents an exciting opportunity to drive innovation in high-performance SoCs and MCUs while collaborating with cross-functional teams to define and implement cutting-edge semiconductor solutions. Key Responsibilities: Define and develop SoC/MCU architecture, translating product requirements into detailed technical specifications. Lead chip implementation, ensuring product compliance through verification, validation, characterization, and testing. Drive automotive SoC/MCU development with expertise in high-performance SoCs, vehicle computers, software-defined vehicles (SDVs), and MCUs. Optimize execution strategies by improving team structures, methodologies, and tools for enhanced efficiency and quality. Evaluate and make strategic decisions on IP selection, including make-versus-buy analysis. Collaborate with system architects, SoC design teams, software engineers, and business leaders to establish common methodologies and best practices. Engage with external stakeholders, manage supplier relationships, participate in technical conferences, and contribute to industry standards. Develop and implement training programs, ensuring the dissemination of best practices and lessons learned. Apply Now! Click on the Apply button or share your resume with Heena at heena.k@randstad.in Tag your connections who might be interested! Join us and shape the future of semiconductor technology!

Kindly share the resume to suhasini.swamy@quest-global.com Job Requirements: Good team player and must be able to work independently. Take the ownership and lead in team building, design, development/porting & validation of system software (Linux, RTOS, Android etc.) in target board. Provide technical inputs to prepare project scope, schedule and cost etc. Guide and mentor the technical leads to deliver commitments on time with Quality. Provide technical solutions for the team Interact with customers on the project technical aspects and prepare and present the project technical progress Co-ordinate and collaborate with onsite support members and communicate the requirements to the offshore team Enhance customer satisfaction by ensuring appropriate engagement Predict project risks and develop mitigation plans Work Experience: Strong C/C++ programming skills Experience in SoC and microcontroller architecture. Good exposure to Linux kernel and driver architecture. Good knowledge in Android internals, Android framework, services, HAL etc. Strong understanding in bootloaders. Experience in RTOS and bare metal firmware design and development activities. Expertise in board bring up, device driver development, interrupt handling etc. Experience in IPs like DMA, CAN, UART, I2C, PCIE, Ethernet, USB, Camera, Display etc. Good debugging skill. Experience in performance and power optimization Experience in Automotive domain. Experience in virtual platform and digital twin. Experience in hypervisors Experience in AutoSAR. Electronics knowledge and basic trouble shooting skills on hardware development boards. • Experience using test equipment to debug the hardware software interface.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 1-3 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Bachelors / Masters degree in electrical or electronics engineering with 1-3 yrs of experience is preferred

Must have expertise in ASIC viterification methodologies and ASIC design flow Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects Experience in any of the listed topics: UVM, formal verification, mixed-signal simulations, power-aware simulations Experience in setting up and debugging functional and/or gate-level simulations Experience in translating functional requirements into verification plans Experience in developing verification environment and regression setup. Coverage analysis and closure

Job Description : Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning. Experience with Verilog, VHDL design Knowledge Experience with C/C++, DPI and System Verilog add on. Experience writing scripts using any languages (Perl, Python, Makefile ) Experience with waveform debug tools, Verdi/SimVision. Knowledge of communication/Interface protocols, like (PCIE, USB ), DDR, SPI Strong communication skills and ability to work as a team Bachelor's degree and a minimum of 5 years relevant industry experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Additional About The Role : As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

About The Role : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications Bachelor Degree in Electrical and Electronics Engineering or Master's Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Working Model This role will require an on-site presence. *

Position: Design Verification Manager Experience: 12+ yrs (IC + People Management) Qualification: B.Tech / B.E or M.Tech / ME in EEE/ECE Job Location: Bangalore Job Type & Shift: Permanent & Day Shift Major Responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Skills & Qualifications Required: 12+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience with ARM/RISCV Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills Kindly Note: We are looking for candidates who can join 15 to 30 days notice max. For more details please feel free to reach out Karthik @ 7658983115 or You may DM your updated profile to: karthik.b@creenosolutions.com