665 Pcie Jobs - Page 17

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

raja.a@honeybeetechsolutions.com resume to Client Name: Proxelera Client SPOC: NA Industry: SEMICON HBTS SPOC: Shilpa Gajjala Client Req ID: ZR_117_JOB Position Name PCIe Driver Development Job No : PROX-14077 Position type: Permanent Total Exp: 2 to 5 Years HBTS Budget: Open No of Position: 1 Notice Period: Within 20 days, Tentative: 27th Jul 2025 Asset: Laptop Mandatory for interview Work Location: Hyderabad Work Type: WFO Job Type: Full-time CVR Type: Internal CVR CVR Panel Name: Shilpa Gajjala Interview Rounds: 2 Rounds Interview Mode: Virtual in Teams Job Description Must have: Must Have -Proficient in C and embedded systems. Must Have -Experience in Linux driver development (PCIe/USB/Ethernet) and application development. Must Have -PCIe driver development experience. Must Have -DMA client/controller driver development experience Must Have -Hands-on experience with Configuration Management tools like GIT, Perforce. Must Have -Have an interest to constantly learn and share new findings. Must Have -Self-motivated Skills required: Must Have -Linux application programming Must Have -Linux device driver development Must Have -Embedded C, MMU, Cache policies Must Have -Excellent debugging skills at kernel and user space and exposure to different debugging tools Must Have -Knowledge on PCIe, Ethernet, TCP, I2C protocols, DMA framework is a plus. Must Have -Make files

raja.a@honeybeetechsolutions.com RESUME SHARE TO CLIENT PROXELERA / SASKEN -Proficient in C and embedded systems. -Experience in Linux driver development (PCIe/USB/Ethernet) and application development. -PCIe driver development experience. -DMA client/controller driver development experience -Hands-on experience with Configuration Management tools like GIT, Perforce. -Have an interest to constantly learn and share new findings. -Self-motivated Skills required: -Linux application programming -Linux device driver development -Embedded C, MMU, Cache policies -Excellent debugging skills at kernel and user space and exposure to different debugging tools -Knowledge on PCIe, Ethernet, TCP, I2C protocols, DMA framework is a plus. -Make files

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: We are looking for an experienced Senior Technical Writer and a skilled Training Content Developer to join our documentation team. In this role, you will lead documentation initiatives, collaborate closely with engineering, product, and customer-facing teams, and create high-quality, user-focused technical content for a range of audiences. The ideal candidate has a strong background in instructional design, adult learning principles, and technical subject matter, along with experience in multimedia content creation and eLearning tools. Your experience will help improve documentation workflows, and enforce content standards. Key Responsibilities: Location: Bangalore Experience: 8+ years Department: Technical Publications / Product Documentation Reports to: Documentation Manager Technical Writing Develop and maintain technical documents such as user guides, API references, application notes, datasheets, product briefs, and troubleshooting guides. Collaborate with engineering, productapps, and support teams to gather information and clarify technical content. Own end-to-end documentation lifecycle: planning, writing, reviewing, publishing, and updating. Define and enforce style guides, templates, and best practices. Lead documentation efforts for new product launches or major feature rollouts. Review and edit content written by other team members for accuracy, clarity, and consistency. Work with tools such as Oxygen XML, DITA, Git, and Bitbucket. Proactively identify content gaps, outdated material, or documentation process improvements. Training Design and develop engaging training materials such as eLearning modules, instructor-led training (ILT) decks, how-to videos, simulations, and assessments. Work closely with subject matter experts (SMEs), product managers, and engineers to gather technical information and translate it into learner-friendly content. Apply instructional design models (e.g., ADDIE, SAM) and adult learning theories to ensure effective knowledge transfer. Create content for various delivery formats online, classroom, blended learning, self-paced, and mobile. Develop and manage content in LMS platforms (e.g., Workday Learning, Moodle, or SAP SuccessFactors). Use tools like Articulate 360, Adobe Captivate, Camtasia, or similar to create multimedia-rich training. Review and update content regularly to keep up with product changes or learner feedback. Analyze learner feedback and assessment data to improve content effectiveness. Required Qualifications: Bachelors or masters degree in engineering with minimum 8 years of experience. Technical writing experience, preferably in semiconductor and EDA domain. Experience in instructional design or training content development. Strong technical aptitude and ability to quickly understand complex concepts. Proven experience with authoring tools like Oxygen XML, MadCap Flare, Confluence, Jira. Familiarity with structured authoring (DITA/XML), version control (Git/Bitbucket). Excellent written and verbal communication skills. Ability to manage multiple projects with minimal supervision. Experience with rapid eLearning development tools and LMS platforms. Strong writing, editing, and visual storytelling skills. Ability to simplify complex technical topics into engaging, digestible learning experiences. Why Join Us Opportunity to work with cutting-edge technology and contribute to innovative products. Collaborative and inclusive work culture. Competitive compensation and benefits package. Career growth through ownership, learning, and mentorship. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTECH/ME/MTECH Or Equivalent Degree EXP7-13years Design Verification role for IP development team. Position is based in Bangalore , part of Cadence IP Group. Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs. In addition to UVM functional verification, role could involve Formal verification of complex design modules. In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs. Understand design and produce detailed verification strategy and test plan. Self-starter and learner with passion for getting the job done on time with great quality. Strong problem solving, analytical and debug skills Excellent verbal and written communications skills We re doing work that matters. Help us solve what others can t.

About this Opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent.

Grow with us About this opportunity We are seeking a Senior FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Join our Team About this opportunity We are seeking a Senior FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768496

Job Description Experience: 3 to 18 years experience. Educational Qualification: B.E./ B.Tech. in Electronics and Communication, Electronics and Telecommunication, M.E. / M.Tech. Electronics & Communication Location: Bangalore Technical/Functional Skill Set : Substantial experience in the field of FPGA based Board Design, Embedded Hardware/Board Design. Expertise in Processor, Networking, Telecommunications, Bus interfaces, DDR memories, Test plan, Board bring-up, Networking, Telecommunications, Serial interfaces, Bus interfaces, DDR Memories Board bring up and debug skills Experience in system level architecture development would be preferred. Embedded HW designs for Defence applications Exposure to qualification process Tools: Schematic capture and layout tools like Orcad/Allegro SI analysis tools Soft Skills: Good Communication Skills People Management and leadership Skills Awareness of Quality Systems. Experience in handling small group sizes and projects Managerial Skills Job Description: To develop and test designs as per the project specification. To review modules developed by the group members. Monitor and Track effort and schedule of the tasks and hardware /software items of the project that are assigned to the group. Coordinate internal project meeting with Project Manager and other Group members, to present any suggestions for improvement Monitor and ensure the quality goals of the group. Co-ordinate Configuration activities and Quality Control Activities Participate, co-ordinate, implement/monitor defect prevention and process improvement activities in the project. Resolve any technical and interpersonal issues of the group members. Assist in annual performance reviews To ensure defect free and timely deliverable as per the project plan. To ensure adherence to defined processes. To provide guidance and technical assistance to Group Members. QMS and Process Adherence Learning and Growth and Group Development

Role & responsibilities - Experience working with high-end SOC, processor and FPGA-based designs - Experience in DDR4/DDR5, DDR4/5, or PCIe gen 3/4/5/6, HDMI, CNVI or Serdes interfaces hardware design - Hands-on experience with Cadence Allegro tools for schematics and PCB layout (CHDL or OrCAD) - Board bring-up experience amd Proficiency in using high-end lab equipment like GHz oscilloscopes, electronic loads, etc

As a member of the NAND & Drive Qualification team, you'll be actively engaged in all phases of the product development cycle with a focus on demonstrating the capabilities of PURE s DFMs. As part of the drive qualification group, your leadership in areas of SSD/NVMe/ OCP spec test, troubleshooting, and analysis of results will be utilized to drive progress with qualification efforts. What you'll be doing: Incorporating tests into a common framework Develop automation support for new test Developing centralized hosting of test output Visualization support for test Support development of metrics Architecture for the above, code for the above, maintenance, effectiveness An overview of your responsibilities includes; Developing Automation Frameworks for SSD Qualification Test suites, Architect & Develop unified test frameworks that Integrate out of the box Test Suites for NVMe/OCP/other SSD standards along with In-house Test suites for SSD Qual Develop Automation support for deploying new SSD Qual tests at scale Use your strong scripting language skills to develop and automate tests and minimize qualification testing cycles Proactively define/develop new SSD qualification tests targeting specific SSD management features and functions, new requirements, exposure to field issues etc Develop, maintain and continuously improve the effectiveness & efficiency of comprehensive qual platform Automated Debug tools to speed up test vs product debug efforts Driving Automation of Data Analysis & Visualization of Qualification test results Develop Automated solutions to Extract, Analyze & Centrally Host Validation data Develop Automated Data Visualization dashboards to help drive Drive Qualification decisions on volume test data at scale Use your background in storage system validation or design to proactively identify, and support the development of metrics Drive improvements in the qualification processes as you observe execution & tool usage Brainstorm methods and procedures to evolve our team s effectiveness Proactively define/develop new SSD qualification tests with focus on OCP spec - features and functions , new requirements, exposure to field issues etc Improve qualification processes that actively enhance efficiency, consistency, reporting and vendor relationships. Participate in various team activities aimed at developing testing process, Perceived as highly skilled In Python based scripting & SW architecture Experienced in leveraging data engineering/science frameworks The ideal candidate would be someone who is a team player and perceived as highly skilled in test development/debugging for hardware/firmware/system validation needs. WHAT you'll NEED TO BRING TO THIS ROLE... 12+ years experience developing software to validate hardware components/systems with strong SW & HW debug skills SW architecture & Solution design experience is desirable Strong knowledge of NAND Flash, Firmware Architecture/Design in Solid State Drive (SSD) or similar storage domain Strong SW Development skills in Python with exposure to OOP; C++ experience is a plus. Knowledge of PCIe/NVMe/OCP, Firmware Architecture/Design in Solid State Drive (SSD) or similar storage domain is a plus Experience in a hardware testing/software testing validation lab for SSDs or Embedded industry segments B.E. or M.E in Electrical Eng, Electronics & Communication Eng, Computer Eng Experience working with complex data models and analysis Experience working at enterprise data storage systems, SSD companies or related component vendors. Experience developing & maintaining CI/CD pipelines for test automation Knowledge/experience with Jenkins & GIT Independent ability to devise, implement, automate and refine qualification methods Strong knowledge of hardware design, storage architectures and storage interfaces Experience with failure modes of flash-based devices WHAT YOU CAN EXPECT FROM US: Pure Innovation : We celebrate those who think critically, like a challenge and aspire to be trailblazers. Pure Growth : We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortunes Best Large Workplaces in the Bay Area , Fortunes Best Workplaces for Millennials and certified as a Great Place to Work ! Pure Team : We build each other up and set aside ego for the greater good

Digital Logic Design: Strong expertise in digital logic design with hands-on experience in RTL coding using Verilog and SystemVerilog. Peripheral Design: Experience in designing high-speed and low-speed peripherals. Design Optimization: Deep understanding of synthesis, timing constraints, clock domain crossing (CDC), and logic optimization techniques. Automation: Proven experience in automating RTL generation for various design Low Power Design: Exposure to low power design techniques, including working with multiple power and clock domains. SoC Integration: Familiarity with ARM SoC, AMBA IP-based designs, and SoC/sub- Protocol Knowledge: Strong knowledge of protocols such as PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, and SPI is highly desired. Expectations from the Role: Communication & Independence: Excellent communication and interpersonal skills, with the ability to work independently. Adaptability: A fast learner who can efficiently operate in a distributed work Initiative & Punctuality: Demonstrates ownership, initiative, and punctuality in all responsibilities. Leadership: Ability to mentor and lead a team to solve complex design challenges.

Digital Logic Design: Strong expertise in digital logic design with hands-on experience in RTL coding using Verilog and SystemVerilog. Peripheral Design: Experience in designing high-speed and low-speed peripherals. Design Optimization: Understanding of synthesis, timing constraints, clock domain crossing (CDC), and logic optimization techniques. Low Power Design: Exposure to low power design techniques, including working with multiple power and clock domains will be advantage. Protocol Knowledge: knowledge of protocols such as PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, and SPI will be preferred. Expectations from the Role: Communication & Independence: Excellent communication and interpersonal skills, with the ability to work independently. Adaptability: A fast learner who can efficiently operate in a distributed work Initiative & Punctuality: Demonstrates ownership, initiative, and punctuality in all

Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 3+ years of relevant experience.Strong in UVM/System Verilog/C/C++/scripting, Simulation, Formal verification. Good understanding of SoC architectures Required Candidate profile GLS verification experience at Core level. SV - UVM understanding. Scripting in perl, python. Debug of complicated designs using Verdi. Power aware verification, SDF / timing simulation.

Job Title: Embedded Software Engineer KEY RESPONSIBILITIES: Development & Testing of Infinity Fabric diagnostic test cases for SoCs Debugging of the test case failures and reporting them to the design team Involvement in test planning of diagnostics Collaboration with various related cross-teams. PREFERRED EXPERIENCE: Expertise in C++ programming Post Silicon diagnostics development & validation Good understanding of data/address bus architecture, caches, memory management. Understanding of PC Hardware, SoC, Chipsets, CPU, GPU, BIOS, firmware etc. Knowledge of x86 / computer architecture Understanding of OS internals Solid knowledge of software development life cycle Strong analytical and problem-solving skills Must be fluent in both written and spoken English. ACADEMIC CREDENTIALS: • Bachelors degree with 7+ years experience or Master’s degree with 5+ years’ experience • Major in Computer science, Electronics, Electricals is preferred. Immediate Joiners preferred 0-30 Days interested candidates send resume to Prasadkaruturi@Mirafra.com

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-EDA #LI-Hybrid

Virtual Walk-In Interview for IT Engineers _Harita Techserv Pvt Ltd Interview Details: Interview Date: 16 -June-25 to 20 -June-25 (Monday to Friday) Interview Timing: 4.00 PM - 7.00 PM Virtual interview link: https://meet.google.com/acb-oniz-gvp Notice Period: Immediate to 30 Days Job Location Bangalore Role: Embedded Firmware Engineer Experience: 10 -12 Years Skills: C/ C++Embedded, RTOS, Multithreading, SPI, UART, PCIe Contact Email ID: yamuna.k@harita.co.in

Grow with us About this opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Primary country and city: India (IN) || Bangalore Req ID: 768495

Grow with us About this opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768495

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Senior Digital Design Engineer - PCIe We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities: Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPs and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows Basic Qualifications / Experience Level: Bachelor s in Electronics/Electrical engineering (Masters preferred). 8+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise: Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes ( Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles . Hands-on experience with processor IP (ARM/ARC) Experience of working on PCIe is a must. Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction. Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes ( 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Preferred Experience: Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus. Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience of working on PCIe/UAL is a big plus. Understanding of PAD design, DFT, and floor planning. Experience in synthesis, and timing closure is a big plus. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

"> Search Jobs Find Jobs For Where Search Jobs ASIC Digital Design, Architect Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 11886 Remote Eligible No Date Posted 11/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly motivated and experienced ASIC Digital Design Architect with a passion for cutting-edge technology and innovation. You thrive in a collaborative environment and have a proven track record of delivering high-quality results in the field of digital design and verification. You possess deep expertise in interface protocols such as Ethernet, PCIe, and CXL, and have a strong understanding of both analog and digital mixed-signal design. Your ability to debug, diagnose, and support complex systems makes you an invaluable asset to any team. You are a problem solver who enjoys tackling challenging technical issues and delivering solutions that exceed expectations. You have a strong foundation in functional verification methodologies, including UVM and System Verilog, and are adept at scripting and automation using tools like Perl and Python. Your excellent communication skills enable you to effectively collaborate with cross-functional teams and support customers in achieving their goals. What You ll Be Doing: - Acting as a technical expert in one or more interface protocols (e.g., Ethernet, PCIe) to support development, verification, silicon validation, and customer support. - Reviewing SERDES/PHY/Controller IP specifications to ensure compliance with relevant protocols. - Developing and reviewing verification plans and environments, with a preference for UVM-based methodologies. - Performing RTL, GLS, and co-simulations, ensuring functional and code coverage closure. - Delivering high-quality RTL and simulation models to customers, along with verification components for integration into their environments. - Supporting customers with IP bring-up in simulation environments and debugging silicon issues post-production. - Demonstrating Testchip+FPGA system demos for customers and at industry conferences. The Impact You Will Have: - Ensuring the successful development and verification of Synopsys multi-protocol 112G PHY IP, a critical component for high-end networking and computing applications. - Driving innovation in the design and validation of industry-leading IP solutions that support multiple electrical standards, including PCIe 6.0, 400G/800G Ethernet, and more. - Enhancing customer satisfaction by delivering high-quality IP and providing exceptional support during integration and silicon bring-up. - Contributing to the advancement of cutting-edge technologies in the Era of Smart Everything, enabling smarter and more connected devices. - Strengthening Synopsys position as a leader in chip design and verification through your technical expertise and innovative solutions. - Representing Synopsys at industry conferences, showcasing the company s capabilities and building strong relationships with customers and partners. What You ll Need: - A B.Tech/M.Tech degree with 15+ years of relevant experience in ASIC design and verification. - Expertise in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. - Proficiency in functional verification methodologies, including VMM, OVM/UVM, and System Verilog. - Experience with System Verilog Assertions, as well as code and functional coverage implementation and review. - Fundamental knowledge of analog and digital mixed-signal design. - Strong scripting and automation skills using Perl and Python. - Excellent debugging and diagnostic skills to identify and resolve complex technical issues. Who You Are: - A collaborative team player with strong communication and interpersonal skills. - A detail-oriented professional with a commitment to delivering high-quality results. - A proactive problem solver who thrives in a fast-paced, dynamic environment. - A lifelong learner who stays up-to-date with the latest industry trends and technologies. - A customer-focused individual who is dedicated to providing exceptional support and building lasting relationships. The Team You ll Be A Part Of: You will join a highly skilled and collaborative team of engineers focused on developing and verifying Synopsys multi-protocol 112G PHY IP. This team leverages leading-edge design, analysis, simulation, and measurement techniques to deliver industry-leading solutions for high-end networking and computing applications. Together, you will drive innovation and shape the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Senior Software Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Senior Software Engineer on our Software Engineering Team in Bangalore. What you ll achieve As a Senior Software Engineer, you will be responsible for developing sophisticated systems and software basis the customer s business goals, needs and general business environment creating software solutions. You will: A BE/ME degree in ECE, CE, CS with 5-8 years of industry experience in System Management software development, strong firmware / System development background with strong C/C++ development/debug skills and Strong in Embedded Linux programming, OS Internals, memory management, IPC, thread programming and embedded application software development. Strong experience in IPMI, DMTF, RedFish, CIM, CIMOM, Linux. Solid understanding of SNMP, IPMI protocols. Experience/exposure to I2C, MCTP, NCSI, PLDM, uEFI protocol is a plus. Working experience with peripheral hardware devices like PCIe Switch, NIC, GPU, FPGA, Memory controller etc. is a plus. Good Knowledge on Storage domain Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Validated knowledge of programming languages; operating systems; firmware; BIOS; device drivers; databases; system, network, operating system, and application administration; embedded software/firmware; tools and utilities Ability to code/debug more sophisticated programs using either written or verbal design specifications Capacity to achieve proficiency of new tools, languages and operating systems with training and on-the-job experience 5-8 years of related experience Desirable Requirements Bachelor s degree Application closing date: 30 June 2025 #NJP

Position: Storage Protocol (like SAS/SATA/NVMe) (CE37ST RM 3295) Responsibility : 3~7 years of experience in firmware development. Desired Skills: Good experience in Implementing solutions for SSD firmware Excellent Coding skills in C and Data Structures. Excellent embedded systems knowledge Exposure to any Storage protocaols like SAS/SATA/NVMe Exposure to other protocols like IPMI, MCTP, NVMe-MI , SMBus, GPIO and I2C Knowledge of Linux kernel and block layer will be added advantage Deep technical understanding of data storage systems preferably NVMe and PCIe would be a very big plus Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 3-7 years Notice period: 0-30 days

About this Opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent.

Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team developing Subsystems & SoCs. You will work the Architecture team to gather the requirements and develop Micro-architecture specifications for one or more SOC Infrastructure areas such as Power management, Debug, Clocks, Resets. Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. You will work with the verification team to review test plans, and help debug design issues. You will work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. You will balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: In addition to bringing your accomplishment of either Bachelors or Master s degree or equivalent experience in Computer Science or Electrical/Computer Engineering. Experience of 5+ years working in design of complex compute subsystems or SoCs, you will need: Expertise in creating Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power management, Debug, Clocks and Resets. Strong knowledge of digital hardware design and Verilog HDL. A thorough understanding and experience of the current design techniques for complex SoC development. Experience leading and developing RTL for Subsystems or SoCs. Conversant with Lint, CDC and RDC flows. Good communication (written, verbal, presentations) skills. Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation #LI-KR2 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm